X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ficecube%2Ficecube.c;h=c027f6f34e61dad7107faf8c723cc83d5367182c;hb=da9d4610d76e52c4d20a8f3d8433439a7fcf5b71;hp=07c25ed8ab5f8b2bb2c673ec64bb88366ec7375a;hpb=64f70bede37f833d2ed31311ff293c759c41a2a6;p=oweals%2Fu-boot.git diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 07c25ed8ab..c027f6f34e 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -27,11 +27,66 @@ #include #include #include +#include -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + +#if defined(CONFIG_LITE5200B) +#include "mt46v32m16.h" #else +# if defined(CONFIG_MPC5200_DDR) +# include "mt46v16m16-75.h" +# else #include "mt48lc16m16a2-75.h" +# endif +#endif + +#ifdef CONFIG_LITE5200B_PM +/* u-boot part of low-power mode implementation */ +#define SAVED_ADDR (*(void **)0x00000000) +#define PSC2_4 0x02 + +void lite5200b_wakeup(void) +{ + unsigned char wakeup_pin; + void (*linux_wakeup)(void); + + /* check PSC2_4, if it's down "QT" is signaling we have a wakeup + * from low power mode */ + *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; + __asm__ volatile ("sync"); + + wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; + if (wakeup_pin & PSC2_4) + return; + + /* acknowledge to "QT" + * by holding pin at 1 for 10 uS */ + *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; + __asm__ volatile ("sync"); + *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; + __asm__ volatile ("sync"); + udelay(10); + + /* put ram out of self-refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ + __asm__ volatile ("sync"); + udelay(10); /* wait a bit */ + + /* jump back to linux kernel code */ + linux_wakeup = SAVED_ADDR; + printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", + linux_wakeup); + linux_wakeup(); +} +#else +#define lite5200b_wakeup() #endif #ifndef CFG_RAMBOOT @@ -86,6 +141,8 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; + #ifndef CFG_RAMBOOT ulong test1, test2; @@ -107,9 +164,9 @@ long int initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -133,10 +190,13 @@ long int initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } if (test1 > test2) { sdram_start(0); dramsize2 = test1; @@ -177,6 +237,26 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + + lite5200b_wakeup(); + return dramsize + dramsize2; } @@ -204,9 +284,9 @@ long int initdram (int board_type) /* find RAM size */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -233,7 +313,9 @@ long int initdram (int board_type) int checkboard (void) { -#if defined(CONFIG_MPC5200) +#if defined (CONFIG_LITE5200B) + puts ("Board: Freescale Lite5200B\n"); +#elif defined(CONFIG_MPC5200) puts ("Board: Motorola MPC5200 (IceCube)\n"); #elif defined(CONFIG_MGT5100) puts ("Board: Motorola MGT5100 (IceCube)\n"); @@ -277,19 +359,17 @@ void pci_init_board(void) } #endif -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } void ide_set_reset (int idereset) @@ -297,11 +377,19 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } } -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +#endif + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif