X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fgdsys%2Fmpc8308%2Fhrcon.c;h=90946cc34e317ee16263a689f73100f7065453a0;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=7e485074ce027bc9165c87e731e9700f70e04476;hpb=470135be276b2d92c6da464c68839202d4ff0d08;p=oweals%2Fu-boot.git diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 7e485074ce..90946cc34e 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -1,15 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ #include +#include +#include #include #include +#include #include -#include +#include +#include #include #include #include @@ -33,16 +36,14 @@ #include -DECLARE_GLOBAL_DATA_PTR; - #define MAX_MUX_CHANNELS 2 enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, + MCFPGA_DONE = BIT(0), + MCFPGA_INIT_N = BIT(1), + MCFPGA_PROGRAM_N = BIT(2), + MCFPGA_UPDATE_ENABLE_N = BIT(3), + MCFPGA_RESET_N = BIT(4), }; enum { @@ -50,7 +51,7 @@ enum { GPIO_MDIO = 1 << 15, }; -unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; struct { @@ -110,7 +111,7 @@ int checkboard(void) printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); - if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -123,12 +124,11 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present = false; + bool ch0_rgmii2_present; FPGA_GET_REG(0, fpga_features, &fpga_features); @@ -140,16 +140,16 @@ int last_stage_init(void) /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; + uint ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); + printf("no done for mclink_controller %u\n", k); break; } } @@ -162,8 +162,10 @@ int last_stage_init(void) } if (hw_type_cat) { + uint mux_ch; int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -182,7 +184,7 @@ int last_stage_init(void) } /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -210,6 +212,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -236,17 +239,17 @@ int last_stage_init(void) * provide access to fpga gpios and controls (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); } -void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); } -int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val; @@ -255,7 +258,7 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; } -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val; @@ -263,7 +266,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); } -void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val; @@ -276,7 +279,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 4, 1); } -void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 4, state ? 0 : 1); } @@ -288,11 +291,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); } -int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 19); } @@ -370,7 +373,7 @@ int ft_board_setup(void *blob, bd_t *bd) */ struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -497,5 +500,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, }; -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);