X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fgateworks%2Fgw_ventana%2Fgw_ventana_spl.c;h=b839b8900f223d37ddceb765568c63a0abe8c262;hb=7f14c31bba70ee339c8c730e263a143b869f2828;hp=668e1122e8d7eeba9a2f248a4939210278b46941;hpb=75f21e3131e33b36c05b7ef1680fec2fc0d3b357;p=oweals%2Fu-boot.git

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 668e1122e8..b839b8900f 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -220,48 +220,30 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  * calibration - these are the various CPU/DDR3 combinations we support
  */
 
-static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00190017,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x43380347,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3C313539,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x36393C39,
-};
-
 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00190017,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x43380347,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3C313539,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x36393C39,
-};
-
-static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl0 = 0x001B0016,
+	.p0_mpwldectrl1 = 0x000C000E,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl0 = 0x4324033A,
+	.p0_mpdgctrl1 = 0x00000000,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3C313539,
+	.p0_mprddlctl = 0x40403438,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x36393C39,
+	.p0_mpwrdlctl = 0x40403D36,
 };
 
 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
 	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00190017,
+	.p0_mpwldectrl0 = 0x00420043,
+	.p0_mpwldectrl1 = 0x0016001A,
 	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0 = 0x43380347,
+	.p0_mpdgctrl0 = 0x4238023B,
+	.p0_mpdgctrl1 = 0x00000000,
 	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl = 0x3C313539,
+	.p0_mprddlctl = 0x40404849,
 	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl = 0x36393C39,
+	.p0_mpwrdlctl = 0x40402E2F,
 };
 
 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
@@ -408,11 +390,12 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 	 *   mx6_ddr_cfg - chip specific timing/layout details
 	 */
 	if (width == 16 && size_mb == 256) {
+		/* 1x 2Gb density chip - same calib as 2x 2Gb */
 		mem = &mt41k128m16jt_125;
 		if (is_cpu_type(MXC_CPU_MX6Q))
-			calib = &mx6dq_128x16_mmdc_calib;
+			calib = &mx6dq_128x32_mmdc_calib;
 		else
-			calib = &mx6sdl_128x16_mmdc_calib;
+			calib = &mx6sdl_128x32_mmdc_calib;
 		debug("2gB density\n");
 	} else if (width == 16 && size_mb == 512) {
 		mem = &mt41k256m16ha_125;