X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Ft4qds%2Fddr.h;h=0b0cc9af39a094b31278461d7ef916f601b8d165;hb=fedae6ebafa79555693e5af1953aacb637ec24b9;hp=d0a0951af9e0950f5df02c958ccdb2a6485ebea0;hpb=3aab0cd852d7c9565c2559a7983cbb73852bac28;p=oweals%2Fu-boot.git

diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index d0a0951af9..0b0cc9af39 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -16,7 +16,7 @@ struct board_specific_parameters {
 	u32 wrlvl_ctl_3;
 	u32 cpo;
 	u32 write_data_delay;
-	u32 force_2T;
+	u32 force_2t;
 };
 
 /*
@@ -25,23 +25,22 @@ struct board_specific_parameters {
  * for each n_ranks group.
  */
 
-#ifdef CONFIG_T4240QDS
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -51,43 +50,18 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
 	{}
 };
 
-#else	/* CONFIG_T4240EMU */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{4,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
-	{2,  2140, 0, 5,     8, 0x0, 0x0,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x0, 0x0,   0xff,    2,  0},
-	{}
-};
-#endif	/* CONFIG_T4240EMU */
-
 /*
  * The three slots have slightly different timing. The center values are good
  * for all slots. We use identical speed tables for them. In future use, if