X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Ft104xrdb%2Feth.c;h=7581a4cdd44b95a685720a3c052064116742ba7b;hb=307367eaffc8638e10ba1784fc66bfe623ae79e2;hp=0188fd4090bf88bd8b253360c81a92cf84846d39;hpb=f763be224fa78893384416734419d8e052c1c5ef;p=oweals%2Fu-boot.git

diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 0188fd4090..7581a4cdd4 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -6,11 +6,13 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
 
 #include "../common/fman.h"
 
@@ -20,6 +22,11 @@ int board_eth_init(bd_t *bis)
 	struct memac_mdio_info memac_mdio_info;
 	unsigned int i;
 	int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
+
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
@@ -41,6 +48,17 @@ int board_eth_init(bd_t *bis)
 			/* T1040RDB only supports SGMII on DTSEC3 */
 			fm_info_set_phy_address(FM1_DTSEC3,
 						CONFIG_SYS_SGMII1_PHY_ADDR);
+			break;
+#endif
+#ifdef CONFIG_T1042RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+			if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+				fm_info_set_phy_address(i, 0);
+			/* T1042RDB only supports SGMII on DTSEC3 */
+			fm_info_set_phy_address(FM1_DTSEC3,
+						CONFIG_SYS_SGMII1_PHY_ADDR);
+			break;
 #endif
 		case PHY_INTERFACE_MODE_RGMII:
 			if (FM1_DTSEC4 == i)
@@ -61,10 +79,58 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_phy_address(i, 0);
 			break;
 		}
-		fm_info_set_mdio(i,
-				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+			fm_info_set_mdio(i, NULL);
+		else
+			fm_info_set_mdio(i,
+					 miiphy_get_dev_by_name(
+							DEFAULT_FM_MDIO_NAME));
+	}
+
+#ifdef CONFIG_VSC9953
+	/* SerDes configured for QSGMII */
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+		for (i = 0; i < 4; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+		for (i = 4; i < 8; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
 	}
 
+	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+		vsc9953_port_enable(8);
+
+	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+		/* Enable L2 On MAC2 using SCFG */
+		struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+				CONFIG_SYS_MPC85xx_SCFG;
+
+		out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+			 (0x80000000));
+		vsc9953_port_enable(9);
+	}
+#endif
+
 	cpu_eth_init(bis);
 #endif