X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Fp1022ds%2Fp1022ds.c;h=aca30f368070e2010278b0084063759e77277369;hb=05f132d74d173854df79bc5541699c3db144e42a;hp=ee93e8b8156f930352253a59b88b75164c9dace2;hpb=a2d12f88129a0a1a7c18630b7a48ade22a48416e;p=oweals%2Fu-boot.git diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index ee93e8b815..aca30f3680 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan * Timur Tabi * @@ -22,9 +22,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -46,6 +46,9 @@ int board_early_init_f(void) /* Set the pin muxing to enable ETSEC2. */ clrbits_be32(&gur->pmuxcr2, 0x001F8000); + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); + return 0; } @@ -53,9 +56,8 @@ int checkboard(void) { u8 sw; - puts("Board: P1022DS "); - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + printf("Board: P1022DS Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); @@ -76,19 +78,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; - - puts(" DDR: "); - return dram_size; -} - #define CONFIG_TFP410_I2C_ADDR 0x38 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ @@ -104,11 +93,19 @@ phys_size_t initdram(int board_type) /* Choose the 11.2896Mhz codec reference clock */ #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 +/* Connect to USB2 */ +#define CONFIG_PIXIS_BRDCFG0_USB2 0x10 +/* Connect to TFM bus */ +#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c +/* Connect to SPI */ +#define CONFIG_PIXIS_BRDCFG0_SPI 0x80 + int misc_init_r(void) { u8 temp; const char *audclk; size_t arglen; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* For DVI, enable the TFP410 Encoder. */ @@ -126,22 +123,48 @@ int misc_init_r(void) return -1; debug("DVI Encoder Read: 0x%02x\n",temp); + /* Enable the USB2 in PMUXCR2 and FGPA */ + if (hwconfig("usb2")) { + clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK, + MPC85xx_PMUXCR2_USB); + setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2); + } + + /* tdm and audio can not enable simultaneous*/ + if (hwconfig("tdm") && hwconfig("audclk")){ + printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n"); + return -1; + } + + /* Enable the TDM in PMUXCR and FGPA */ + if (hwconfig("tdm")) { + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK, + MPC85xx_PMUXCR_TDM); + setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM); + /* TDM need some configration option by SPI */ + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK, + MPC85xx_PMUXCR_SPI); + setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI); + } + /* * Enable the reference clock for the WM8776 codec, and route the MUX * pins for SSI. The default is the 12.288 MHz clock */ - temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | - CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); - temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; - - audclk = hwconfig_arg("audclk", &arglen); - /* Check the first two chars only */ - if (audclk && (strncmp(audclk, "11", 2) == 0)) - temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; - else - temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; - out_8(&pixis->brdcfg1, temp); + if (hwconfig("audclk")) { + temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | + CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); + temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; + + audclk = hwconfig_arg("audclk", &arglen); + /* Check the first two chars only */ + if (audclk && (strncmp(audclk, "11", 2) == 0)) + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; + else + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; + setbits_8(&pixis->brdcfg1, temp); + } return 0; } @@ -200,7 +223,7 @@ static u8 serdes_dev_slot[][SATA2 + 1] = { * Returns the name of the slot to which the PCIe or SATA controller is * connected */ -const char *serdes_slot_name(enum srds_prtcl device) +const char *board_serdes_name(enum srds_prtcl device) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); @@ -215,73 +238,10 @@ const char *serdes_slot_name(enum srds_prtcl device) return "Nothing"; } -static void configure_pcie(struct fsl_pci_info *info, - struct pci_controller *hose, - const char *connected) -{ - static int bus_number = 0; - int is_endpoint; - - set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); - set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); - is_endpoint = fsl_setup_hose(hose, info->regs); - printf(" PCIE%u connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); - bus_number = fsl_pci_init_port(info, hose, bus_number); -} - -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pci_info pci_info; - u32 devdisr = in_be32(&gur->devdisr); - -#ifdef CONFIG_PCIE1 - if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info, 1); - configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); - } else { - printf(" PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info, 2); - configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); - } else { - printf(" PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info, 3); - configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); - } else { - printf(" PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif + fsl_pcie_init_board(0); } #endif @@ -319,6 +279,7 @@ int board_early_init_r(void) */ int board_eth_init(bd_t *bis) { + struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; unsigned int num = 0; @@ -331,6 +292,10 @@ int board_eth_init(bd_t *bis) num++; #endif + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); } @@ -339,7 +304,8 @@ int board_eth_init(bd_t *bis) * ft_codec_setup - fix up the clock-frequency property of the codec node * * Update the clock-frequency property based on the value of the 'audclk' - * hwconfig option. If audclk is not specified, then default to 12.288MHz. + * hwconfig option. If audclk is not specified, then don't write anything + * to the device tree, because it means that the codec clock is disabled. */ static void ft_codec_setup(void *blob, const char *compatible) { @@ -348,12 +314,15 @@ static void ft_codec_setup(void *blob, const char *compatible) u32 freq; audclk = hwconfig_arg("audclk", &arglen); - if (audclk && (strncmp(audclk, "11", 2) == 0)) - freq = 11289600; - else - freq = 12288000; - - do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); + if (audclk) { + if (strncmp(audclk, "11", 2) == 0) + freq = 11289600; + else + freq = 12288000; + + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", + freq, 1); + } } void ft_board_setup(void *blob, bd_t *bd) @@ -378,10 +347,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_codec_setup(blob, "wlf,wm8776"); } #endif - -#ifdef CONFIG_MP -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif