X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8315erdb%2Fmpc8315erdb.c;h=5dc558a4f8fafeadeacae6603dc16285536710d2;hb=6aa3d3bfaa986f1aff5e21a9b9f68d087715b1a9;hp=dea4d6fe7afdd45c2cd6511f79b396dc2ca347d7;hpb=cb32ed1fc298875845f166d326a3f2704a0d5364;p=oweals%2Fu-boot.git

diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index dea4d6fe7a..5dc558a4f8 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -32,6 +32,8 @@
 #include <mpc83xx.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,6 +47,8 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifndef CONFIG_NAND_SPL
+
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -136,7 +140,6 @@ void pci_init_board(void)
 	volatile law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *reg[] = { pci_regions };
 	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-	int warmboot;
 
 	/* Enable all 3 PCI_CLK_OUTPUTs. */
 	clk->occr |= 0xe0000000;
@@ -150,10 +153,7 @@ void pci_init_board(void)
 	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
-	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
-	warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
-
-	mpc83xx_pci_init(1, reg, warmboot);
+	mpc83xx_pci_init(1, reg);
 
 	/* Configure the clock for PCIE controller */
 	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
@@ -171,7 +171,7 @@ void pci_init_board(void)
 	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
 	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
 
-	mpc83xx_pcie_init(2, pcie_reg, warmboot);
+	mpc83xx_pcie_init(2, pcie_reg);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
@@ -220,3 +220,41 @@ int board_eth_init(bd_t *bis)
 	cpu_eth_init(bis);	/* Initialize TSECs first */
 	return pci_eth_init(bis);
 }
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8315ERDB\n");
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+		      CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */