X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8313erdb%2Fsdram.c;h=99f6bcd5a933b2e78ba0ea6c1531c83a32b32209;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=3a6347fe1a5533ae38ada6af28dcd16677b28e99;hpb=e4c09508545d1c45617ba45391c03c03cbc360b9;p=oweals%2Fu-boot.git diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 3a6347fe1a..99f6bcd5a9 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -1,32 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 * * Authors: Nick.Spence@freescale.com * Wilson.Lo@freescale.com * scottwood@freescale.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include +#include #include #include +#include #include #include @@ -35,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { u32 magic = *(u32 *)0; @@ -58,46 +43,52 @@ static void resume_from_sleep(void) */ static long fixed_sdram(void) { - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; -#ifndef CFG_RAMBOOT - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; /* * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; else #endif - im->ddr.sdram_cfg = CFG_SDRAM_CFG; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); /* enable DDR controller */ @@ -107,28 +98,31 @@ static long fixed_sdram(void) return msize; } -phys_size_t initdram(int board_type) +int dram_init(void) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc = &im->lbus; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; + return -ENXIO; /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF); + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; sync(); -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) resume_from_sleep(); #endif /* return total bus SDRAM size(bytes) -- DDR */ - return msize; + gd->ram_size = msize; + + return 0; }