X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8308rdb%2Fmpc8308rdb.c;h=259d6aa1c2c9b3a9b305be96bead318d33650fb5;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=a864189571a793f32b06c31cb17046892b525af2;hpb=9efac4a1eb99d9c5539aa6992025eeacab7980c6;p=oweals%2Fu-boot.git

diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index a864189571..259d6aa1c2 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -1,50 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
 #include <hwconfig.h>
 #include <i2c.h>
-#include <libfdt.h>
+#include <init.h>
+#include <net.h>
+#include <spi.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
 #include <pci.h>
 #include <mpc83xx.h>
 #include <vsc7385.h>
 #include <netdev.h>
+#include <fsl_esdhc.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_mpc83xx_serdes.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK	0x00400000
 
-int board_early_init_f(void)
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
-	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	return bus == 0 && cs == 0;
+}
 
-	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
-		gd->flags |= GD_FLG_SILENT;
+void spi_cs_activate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 
-	return 0;
+	/* active low */
+	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* inactive high */
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
 }
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
 
 static u8 read_board_info(void)
 {
@@ -96,16 +108,12 @@ void pci_init_board(void)
 {
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	sysconf83xx_t *sysconf = &immr->sysconf;
-	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
 	law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *pcie_reg[] = { pcie_regions_0 };
 
 	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
 					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
 
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
-				    SCCR_PCIEXP1CM_1);
-
 	/* Deassert the resets in the control register */
 	out_be32(&sysconf->pecr1, 0xE0008000);
 	udelay(2000);
@@ -114,7 +122,7 @@ void pci_init_board(void)
 	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
 	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
 
-	mpc83xx_pcie_init(1, pcie_reg, 0);
+	mpc83xx_pcie_init(1, pcie_reg);
 }
 /*
  * Miscellaneous late-boot configurations
@@ -123,6 +131,25 @@ void pci_init_board(void)
 */
 int misc_init_r(void)
 {
+#ifdef CONFIG_MPC8XXX_SPI
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+
+	/*
+	 * Set proper bits in SICRH to allow SPI on header J8
+	 *
+	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+	 * switch. The pinmux configuration does not have a fine enough
+	 * granularity to support both simultaneously.
+	 */
+	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+	/* Set header J8 SPI chip select output, disabled */
+	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
 #ifdef CONFIG_VSC7385_IMAGE
 	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 		CONFIG_VSC7385_IMAGE_SIZE)) {
@@ -134,10 +161,13 @@ int misc_init_r(void)
 	return 0;
 }
 #if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
+
+	return 0;
 }
 #endif
 
@@ -146,12 +176,14 @@ int board_eth_init(bd_t *bis)
 	int rv, num_if = 0;
 
 	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize TSECs.\n");
 
-	if ((rv = pci_eth_init(bis)) >= 0)
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
 		num_if += rv;
 	else
 		printf("ERROR: failed to initialize PCI Ethernet.\n");