X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Ffreescale%2Fcorenet_ds%2Fcorenet_ds.c;h=60e2100af3089144759b42f6ed66d82bc15ae96c;hb=e20cc2ca15b5b0644f51b6e58d530d70acd2bc00;hp=3cdefb34efc1214212a64f2c1617d9a6d8f34467;hpb=3df4f46f3209c067dcadc969ed02d27c97fa3632;p=oweals%2Fu-boot.git diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3cdefb34ef..60e2100af3 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -1,50 +1,37 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include +#include #include #include #include #include #include -#include #include #include #include - -extern void pci_of_setup(void *blob, bd_t *bd); +#include #include "../common/ngpixis.h" +#include "corenet_ds.h" DECLARE_GLOBAL_DATA_PTR; -void cpu_mp_lmb_reserve(struct lmb *lmb); - int checkboard (void) { u8 sw; - struct cpu_type *cpu = gd->cpu; + struct cpu_type *cpu = gd->arch.cpu; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ + defined(CONFIG_P5040DS) + unsigned int i; +#endif + static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", @@ -62,10 +49,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); -#ifdef CONFIG_PHYS_64BIT - puts("36-bit Addressing\n"); -#endif - /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the @@ -74,10 +57,29 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } +#ifdef CONFIG_P5040DS + /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ + sw = in_8(&PIXIS_SW(9)); + printf("Bank4=%sMhz ", freq[sw & 3]); +#endif + puts("\n"); +#else sw = in_8(&PIXIS_SW(3)); - printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); - printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); - printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); + /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ + /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ + /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ + printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); + printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); + printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); +#endif return 0; } @@ -118,28 +120,8 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); - -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ #endif return 0; @@ -155,7 +137,7 @@ static const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_156_25: return "156.25"; default: - return "???"; + return "150"; } } @@ -166,19 +148,42 @@ int misc_init_r(void) serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; - u8 sw3; + u8 sw; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } +#else /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ - sw3 = in_8(&PIXIS_SW(3)); - actual[0] = (sw3 & 0x40) ? + sw = in_8(&PIXIS_SW(3)); + actual[0] = (sw & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw3 & 0x20) ? + actual[1] = (sw & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw3 & 0x10) ? + actual[2] = (sw & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; +#endif for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; @@ -193,45 +198,6 @@ int misc_init_r(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - - setup_ddr_tlbs(dram_size / 0x100000); - - puts(" DDR: "); - return dram_size; -} - -#ifdef CONFIG_MP -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif - -void ft_srio_setup(void *blob) -{ -#ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); -#endif -#ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); -#endif -} - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -239,8 +205,6 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); - ft_srio_setup(blob); - base = getenv_bootm_low(); size = getenv_bootm_size(); @@ -251,9 +215,10 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_liodn(blob); -} + fdt_fixup_dr_usb(blob, bd); -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif }