X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fesd%2Fcpci750%2Fcpci750.c;h=298aa6a195f6bca3fb6e216cb4296e1580354836;hb=9c73f4b81172bc9f1b8f132450e69bcfb5b960ca;hp=56c12d7317da68d41ea22bde967b8923d770b0f0;hpb=771e05be07589ca159d361142387e03fd26d2f6d;p=oweals%2Fu-boot.git diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 56c12d7317..298aa6a195 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -29,6 +29,7 @@ */ #include +#include #include <74xx_7xx.h> #include "../../Marvell/include/memory.h" #include "../../Marvell/include/pci.h" @@ -54,8 +55,74 @@ #define DP(x) #endif +static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ + {"PCI0DLL_1 "}, /* 30 */ + {"PCI0DLL_0 "}, /* 29 */ + {"PCI1DLL_2 "}, /* 28 */ + {"PCI1DLL_1 "}, /* 27 */ + {"PCI1DLL_0 "}, /* 26 */ + {"BbEP2En "}, /* 25 */ + {"SDRAMRdDataDel"}, /* 24 */ + {"SDRAMRdDel "}, /* 23 */ + {"SDRAMSync "}, /* 22 */ + {"SDRAMPipeSel_1"}, /* 21 */ + {"SDRAMPipeSel_0"}, /* 20 */ + {"SDRAMAddDel "}, /* 19 */ + {"SDRAMClkSel "}, /* 18 */ + {"Reserved(1!) "}, /* 17 */ + {"PCIRty "}, /* 16 */ + {"BootCSWidth_1 "}, /* 15 */ + {"BootCSWidth_0 "}, /* 14 */ + {"PCI1PadsCal "}, /* 13 */ + {"PCI0PadsCal "}, /* 12 */ + {"MultiMVId_1 "}, /* 11 */ + {"MultiMVId_0 "}, /* 10 */ + {"MultiGTEn "}, /* 09 */ + {"Int60xArb "}, /* 08 */ + {"CPUBusConfig_1"}, /* 07 */ + {"CPUBusConfig_0"}, /* 06 */ + {"DefIntSpc "}, /* 05 */ + {0 }, /* 04 */ + {"SROMAdd_1 "}, /* 03 */ + {"SROMAdd_0 "}, /* 02 */ + {"DRAMPadCal "}, /* 01 */ + {"SInitEn "}, /* 00 */ + {0 }, /* 31 */ + {0 }, /* 30 */ + {0 }, /* 29 */ + {0 }, /* 28 */ + {0 }, /* 27 */ + {0 }, /* 26 */ + {0 }, /* 25 */ + {0 }, /* 24 */ + {0 }, /* 23 */ + {0 }, /* 22 */ + {"JTAGCalBy "}, /* 21 */ + {"GB2Sel "}, /* 20 */ + {"GB1Sel "}, /* 19 */ + {"DRAMPLL_MDiv_5"}, /* 18 */ + {"DRAMPLL_MDiv_4"}, /* 17 */ + {"DRAMPLL_MDiv_3"}, /* 16 */ + {"DRAMPLL_MDiv_2"}, /* 15 */ + {"DRAMPLL_MDiv_1"}, /* 14 */ + {"DRAMPLL_MDiv_0"}, /* 13 */ + {"GB0Sel "}, /* 12 */ + {"DRAMPLLPU "}, /* 11 */ + {"DRAMPLL_HIKVCO"}, /* 10 */ + {"DRAMPLLNP "}, /* 09 */ + {"DRAMPLL_NDiv_7"}, /* 08 */ + {"DRAMPLL_NDiv_6"}, /* 07 */ + {"CPUPadCal "}, /* 06 */ + {"DRAMPLL_NDiv_5"}, /* 05 */ + {"DRAMPLL_NDiv_4"}, /* 04 */ + {"DRAMPLL_NDiv_3"}, /* 03 */ + {"DRAMPLL_NDiv_2"}, /* 02 */ + {"DRAMPLL_NDiv_1"}, /* 01 */ + {"DRAMPLL_NDiv_0"}}; /* 00 */ + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); +extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ @@ -363,6 +430,21 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif + if (flash_info[3].size < CFG_FLASH_INCREMENT) { + unsigned int flash_offset; + unsigned int l; + + flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + if (flash_info[3].start[l] != 0) { + flash_info[3].start[l] += flash_offset; + } + } + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + } return 0; } @@ -486,7 +568,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) { asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ + : : : "fr0"); /* Clobbers fr0 */ return; } @@ -494,18 +576,18 @@ static void move64 (unsigned long long *src, unsigned long long *dest) #if defined (CFG_DRAM_TEST_DATA) unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaa, - 0xcccccccccccccccc, - 0xf0f0f0f0f0f0f0f0, - 0xff00ff00ff00ff00, - 0xffff0000ffff0000, - 0xffffffff00000000, - 0x00000000ffffffff, - 0x0000ffff0000ffff, - 0x00ff00ff00ff00ff, - 0x0f0f0f0f0f0f0f0f, - 0x3333333333333333, - 0x5555555555555555 + 0xaaaaaaaaaaaaaaaaLL, + 0xccccccccccccccccLL, + 0xf0f0f0f0f0f0f0f0LL, + 0xff00ff00ff00ff00LL, + 0xffff0000ffff0000LL, + 0xffffffff00000000LL, + 0x00000000ffffffffLL, + 0x0000ffff0000ffffLL, + 0x00ff00ff00ff00ffLL, + 0x0f0f0f0f0f0f0f0fLL, + 0x3333333333333333LL, + 0x5555555555555555LL, }; /*********************************************************************/ @@ -555,7 +637,7 @@ unsigned long long pattern[] = { int mem_test_data (void) { unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; - unsigned long long temp64; + unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; unsigned int hi, lo; @@ -564,9 +646,9 @@ int mem_test_data (void) move64 (&(pattern[i]), pmem); move64 (pmem, &temp64); - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ hi = (pattern[i] >> 32) & 0xffffffff; lo = pattern[i] & 0xffffffff; @@ -662,7 +744,7 @@ int mem_march (volatile unsigned long long *base, unsigned long long wmask, short read, short write) { unsigned int i; - unsigned long long temp; + unsigned long long temp = 0; unsigned int hitemp, lotemp, himask, lomask; for (i = 0; i < size; i++) { @@ -839,11 +921,11 @@ int testdram (void) } #endif /* CFG_DRAM_TEST */ -/* ronen - the below functions are used by the bootm function */ +/* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ /* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ +/* the kernel data areas. */ +/* - we diable and invalidate the icache and dcache. */ void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) { u32 temp; @@ -883,3 +965,38 @@ void board_prebootm_init () flush_data_cache (); dcache_disable (); } + +int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int reset_sample_low; + unsigned int reset_sample_high; + unsigned int l, l1, l2; + + GT_REG_READ(0x3c4, &reset_sample_low); + GT_REG_READ(0x3d4, &reset_sample_high); + printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); + + l2 = 0; + for (l=0; l<63; l++) { + if (show_config_tab[l][0] != 0) { + printf("%14s:%1x ", show_config_tab[l], + ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); + l2++; + if ((l2 % 4) == 0) + printf("\n"); + } else { + l1++; + } + if (l == 32) + reset_sample_low = reset_sample_high; + } + printf("\n"); + + return(0); +} + +U_BOOT_CMD( + show_config, 1, 1, do_show_config, + "show_config - Show Marvell strapping register\n", + "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" + );