X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fesd%2Fapc405%2Fapc405.c;h=46622a29fd42688219bcb239cb8da35ee74eb868;hb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;hp=e629fd94913ad7c213dc7a74be71fe4e331dea3d;hpb=ce42d166ac3c55ebf1e7c2f9707a79acefa006be;p=oweals%2Fu-boot.git

diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index e629fd9491..46622a29fd 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -41,7 +41,7 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 extern void lxt971_no_sleep(void);
 extern ulong flash_get_size (ulong base, int banknum);
 
-int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
+int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
 
 /* fpga configuration data - gzip compressed and generated by bin2c */
 const unsigned char fpgadata[] =
@@ -92,16 +92,16 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 
 int board_revision(void)
 {
-	unsigned long cntrl0Reg;
-	volatile unsigned long value;
+	unsigned long CPC0_CR0Reg;
+	unsigned long value;
 
 	/*
 	 * Get version of APC405 board from GPIO's
 	 */
 
 	/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
-	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x03800000);
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
 	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
 	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
 
@@ -113,7 +113,7 @@ int board_revision(void)
 	/*
 	 * Restore GPIO settings
 	 */
-	mtdcr(cntrl0, cntrl0Reg);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
 	switch (value) {
 	case 0x001c0000:
@@ -140,7 +140,7 @@ int board_early_init_f (void)
 	 * First pull fpga-prg pin low, to disable fpga logic
 	 */
 	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
-	out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output   */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
 	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
 
 	/*
@@ -166,7 +166,7 @@ int board_early_init_f (void)
 	/*
 	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
 	 */
-	mtebc(epcr, 0xa8400000); /* ebc always driven */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 
 	/*
 	 * New boards have a single 32MB flash connected to CS0
@@ -174,12 +174,12 @@ int board_early_init_f (void)
 	 */
 	if (board_revision() >= 8) {
 		/* disable CS1 */
-		mtebc(pb1ap, 0);
-		mtebc(pb1cr, 0);
+		mtebc(PB1AP, 0);
+		mtebc(PB1CR, 0);
 
 		/* resize CS0 to 32MB */
-		mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
-		mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
+		mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+		mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
 	}
 
 	return 0;
@@ -200,8 +200,8 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
-	u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
-	u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
 	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
 	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
 	unsigned char *dst;
@@ -209,7 +209,7 @@ int misc_init_r(void)
 	int status;
 	int index;
 	int i;
-	unsigned long cntrl0Reg;
+	unsigned long CPC0_CR0Reg;
 	char *str;
 	uchar *logo_addr;
 	ulong logo_size;
@@ -219,11 +219,11 @@ int misc_init_r(void)
 	/*
 	 * Setup GPIO pins (CS6+CS7 as GPIO)
 	 */
-	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+	CPC0_CR0Reg = mfdcr(CPC0_CR0);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset(NULL, 0, 0, NULL);
 	}
@@ -265,7 +265,7 @@ int misc_init_r(void)
 	}
 
 	/* restore gpio/cs settings */
-	mtdcr(cntrl0, cntrl0Reg);
+	mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
 	puts("FPGA:  ");
 
@@ -297,11 +297,11 @@ int misc_init_r(void)
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
-	out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
+	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 	for (i=0;i<100;i++)
 		udelay(1000);
 	udelay(1000);
-	out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
+	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -315,15 +315,15 @@ int misc_init_r(void)
 	str = getenv("splashimage");
 	if (str) {
 		logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
-		logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
+		logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 	} else {
 		logo_addr = logo_bmp;
 		logo_size = sizeof(logo_bmp);
 	}
 
 	if (gd->board_type >= 6) {
-		result = lcd_init((uchar *)CFG_LCD_BIG_REG,
-				  (uchar *)CFG_LCD_BIG_MEM,
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				  regs_13505_640_480_16bpp,
 				  sizeof(regs_13505_640_480_16bpp) /
 				  sizeof(regs_13505_640_480_16bpp[0]),
@@ -332,16 +332,16 @@ int misc_init_r(void)
 			/* retry with internal image */
 			logo_addr = logo_bmp;
 			logo_size = sizeof(logo_bmp);
-			lcd_init((uchar *)CFG_LCD_BIG_REG,
-				 (uchar *)CFG_LCD_BIG_MEM,
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				 regs_13505_640_480_16bpp,
 				 sizeof(regs_13505_640_480_16bpp) /
 				 sizeof(regs_13505_640_480_16bpp[0]),
 				 logo_addr, logo_size);
 		}
 	} else {
-		result = lcd_init((uchar *)CFG_LCD_BIG_REG,
-				  (uchar *)CFG_LCD_BIG_MEM,
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				  regs_13806_640_480_16bpp,
 				  sizeof(regs_13806_640_480_16bpp) /
 				  sizeof(regs_13806_640_480_16bpp[0]),
@@ -350,8 +350,8 @@ int misc_init_r(void)
 			/* retry with internal image */
 			logo_addr = logo_bmp;
 			logo_size = sizeof(logo_bmp);
-			lcd_init((uchar *)CFG_LCD_BIG_REG,
-				 (uchar *)CFG_LCD_BIG_MEM,
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				 regs_13806_640_480_16bpp,
 				 sizeof(regs_13806_640_480_16bpp) /
 				 sizeof(regs_13806_640_480_16bpp[0]),
@@ -389,12 +389,12 @@ int misc_init_r(void)
 	 * fix environment for field updated units
 	 */
 	if (getenv("altbootcmd") == NULL) {
-		setenv("usb_load", CFG_USB_LOAD_COMMAND);
-		setenv("usbargs", CFG_USB_ARGS);
+		setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+		setenv("usbargs", CONFIG_SYS_USB_ARGS);
 		setenv("bootcmd", CONFIG_BOOTCOMMAND);
-		setenv("usb_self", CFG_USB_SELF_COMMAND);
-		setenv("bootlimit", CFG_BOOTLIMIT);
-		setenv("altbootcmd", CFG_ALT_BOOTCOMMAND);
+		setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+		setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+		setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
 		saveenv();
 	}
 
@@ -426,17 +426,17 @@ int checkboard (void)
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
-	u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
 	if (on) {
 		out_be16(fpga_mode,
-			 in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
+			 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	} else {
 		out_be16(fpga_mode,
-			 in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
+			 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	}
 }
 #endif /* CONFIG_IDE_RESET */
@@ -449,7 +449,7 @@ void reset_phy(void)
 	lxt971_no_sleep();
 }
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 int usb_board_init(void)
 {
 	return 0;
@@ -480,4 +480,4 @@ int usb_board_init_fail(void)
 	usb_board_stop();
 	return 0;
 }
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */