X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Fcompal%2Fpaz00%2Fpaz00.c;h=64d0860d213944d198220c9ae9c70655d6d8a570;hb=60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22;hp=0c09ce0a4640b373c4afc3e2ac8157d114520e89;hpb=ffec1eb9c7a88db4be06dbf596fc8578e4586b62;p=oweals%2Fu-boot.git diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 0c09ce0a46..64d0860d21 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -1,81 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. */ #include +#include #include -#include +#include #include -#include #include -#ifdef CONFIG_TEGRA2_MMC -#include -#endif - -/* - * Routine: gpio_config_uart - * Description: Does nothing on Paz00 - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_MMC_SDHCI_TEGRA /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { /* SDMMC4: config 3, x8 on 2nd set of pins */ - pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); - pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PINGRP_ATB); - pinmux_tristate_disable(PINGRP_GMA); - pinmux_tristate_disable(PINGRP_GME); + pinmux_tristate_disable(PMUX_PINGRP_ATB); + pinmux_tristate_disable(PMUX_PINGRP_GMA); + pinmux_tristate_disable(PMUX_PINGRP_GME); /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDIO1); + pinmux_tristate_disable(PMUX_PINGRP_SDIO1); /* For power GPIO PV1 */ - pinmux_tristate_disable(PINGRP_UAC); + pinmux_tristate_disable(PMUX_PINGRP_UAC); /* For CD GPIO PV5 */ - pinmux_tristate_disable(PINGRP_GPV); + pinmux_tristate_disable(PMUX_PINGRP_GPV); } +#endif +#ifdef CONFIG_DM_VIDEO /* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) +void pin_mux_display(void) { - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 4-bit bus */ - /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra2_mmc_init(0, 4, -1, -1); - - debug("board_mmc_init: init SD slot\n"); - /* init dev 3, SD slot, with 4-bit bus */ - tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); + debug("init display pinmux\n"); - return 0; + /* EN_VDD_PANEL GPIO A4 */ + pinmux_tristate_disable(PMUX_PINGRP_DAP2); } #endif