X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Famcc%2Fsequoia%2Fsequoia.c;h=ba365aea3188e33a5b0f26dc2025206e94746454;hb=18d156eb37c90fadc8ec7a81a3b89176161f85b7;hp=95734b9c57c347bc3fa25579dc98f3edc4da0e59;hpb=afa98843e4665add11b69496341053b268156e3a;p=oweals%2Fu-boot.git

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 95734b9c57..ba365aea31 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2006
  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -31,11 +31,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+ulong flash_get_size (ulong base, int banknum);
+
 int board_early_init_f(void)
 {
-	unsigned long sdr0_cust0;
-	unsigned long sdr0_pfc1, sdr0_pfc2;
-	register uint reg;
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
 
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xb8400000);
@@ -123,12 +125,12 @@ int board_early_init_f(void)
 
 	/* setup NAND FLASH */
 	mfsdr(SDR0_CUST0, sdr0_cust0);
-        sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
 		SDR0_CUST0_NDFC_ENABLE		|
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
 		(0x80000000 >> (28 + CFG_NAND_CS));
-        mtsdr(SDR0_CUST0, sdr0_cust0);
+	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	return 0;
 }
@@ -140,16 +142,24 @@ int misc_init_r(void)
 {
 	uint pbcr;
 	int size_val = 0;
+	u32 reg;
+#ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
 	char *act = getenv("usbact");
+#endif
 
 	/*
 	 * FLASH stuff...
 	 */
 
 	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	mtdcr(ebccfga, pb3cr);
 #else
@@ -190,9 +200,10 @@ int misc_init_r(void)
 #endif
 	mtdcr(ebccfgd, pbcr);
 
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
 
 #ifdef CFG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
@@ -211,40 +222,41 @@ int misc_init_r(void)
 	/*
 	 * USB suff...
 	 */
+#ifdef CONFIG_440EPX
 	if (act == NULL || strcmp(act, "hostdev") == 0)	{
 		/* SDR Setting */
-        	mfsdr(SDR0_PFC1, sdr0_pfc1);
-        	mfsdr(SDR0_USB0, usb2d0cr);
-        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-        	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
 
 		/* An 8-bit/60MHz interface is the only possible alternative
 		   when connecting the Device to the PHY */
-        	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
 
-        	/* To enable the USB 2.0 Device function through the UTMI interface */
-        	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
+		/* To enable the USB 2.0 Device function through the UTMI interface */
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
 
-        	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
 
-        	mtsdr(SDR0_PFC1, sdr0_pfc1);
-        	mtsdr(SDR0_USB0, usb2d0cr);
-        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
 		/*clear resets*/
 		udelay (1000);
@@ -261,11 +273,11 @@ int misc_init_r(void)
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
 		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
 		udelay (1000);
@@ -284,33 +296,33 @@ int misc_init_r(void)
 		/*-------------------PATCH-------------------------------*/
 
 		/* SDR Setting */
-        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mfsdr(SDR0_USB2H0CR, usb2h0cr);
 		mfsdr(SDR0_USB0, usb2d0cr);
 		mfsdr(SDR0_PFC1, sdr0_pfc1);
 
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;	/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
 		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
 
 		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
+		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
 
 		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
+		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
 
 		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
+		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
 
-        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB2H0CR, usb2h0cr);
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 		mtsdr(SDR0_USB0, usb2d0cr);
 		mtsdr(SDR0_PFC1, sdr0_pfc1);
 
@@ -322,6 +334,19 @@ int misc_init_r(void)
 
 		printf("USB:   Device(int phy)\n");
 	}
+#endif /* CONFIG_440EPX */
+
+	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
+	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+	mtsdr(SDR0_SRST1, reg);
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+	mtdcr(plb4_acr, reg);
 
 	return 0;
 }
@@ -329,8 +354,19 @@ int misc_init_r(void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+	u8 val;
 
+#ifdef CONFIG_440EPX
 	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+#else
+	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
+#endif
+
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
+	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);