X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Famcc%2Fkilauea%2Fkilauea.c;h=f30dc8f92411126fd5ae0abb2e22cd55d7ce5870;hb=794a5924972fc8073616e98a2668da4a5f9aea90;hp=b59bd6fc0e237f50d3db20eb373b381043732e2a;hpb=d4cb2d17946466740afeb195a57d6cb290bf4cc0;p=oweals%2Fu-boot.git diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index b59bd6fc0e..f30dc8f924 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -25,8 +25,9 @@ #include #include #include +#include #include -#include +#include #if defined(CONFIG_PCI) #include @@ -37,14 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -void fpga_init(void) -{ - /* - * Set FPGA regs - */ - out32(CFG_FPGA_BASE, 0xff570cc0); -} - /* * Board early initialization function */ @@ -199,8 +192,6 @@ int board_early_init_f (void) */ mtsdr(SDR0_SRST, 0); - fpga_init(); - /* Configure 405EX for NAND usage */ val = SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | @@ -209,6 +200,20 @@ int board_early_init_f (void) (0x80000000 >> (28 + CFG_NAND_CS)); mtsdr(SDR0_CUST0, val); + /* + * Configure PFC (Pin Function Control) registers + * -> Enable USB + */ + val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + return 0; } @@ -225,11 +230,46 @@ int misc_init_r(void) return 0; } +static int is_405exr(void) +{ + u32 pvr = get_pvr(); + + if (pvr & 0x00000004) + return 0; /* bit 2 set -> 405EX */ + + return 1; /* bit 2 cleared -> 405EXr */ +} + +int board_emac_count(void) +{ + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if (is_405exr()) + return 1; + else + return 2; +} + +static int board_pcie_count(void) +{ + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if (is_405exr()) + return 1; + else + return 2; +} + int checkboard (void) { char *s = getenv("serial#"); - printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); + if (is_405exr()) + printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); + else + printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); if (s != NULL) { puts(", serial# "); @@ -259,45 +299,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - #ifdef CONFIG_PCI static struct pci_controller pcie_hose[2] = {{0},{0}}; @@ -310,17 +311,15 @@ void pcie_setup_hoses(int busno) char *env; unsigned int delay; - for (i = 0; i < 2; i++) { + for (i = 0; i < board_pcie_count(); i++) { - if (is_end_point(i)) { - printf("PCIE%d: will be configured as endpoint\n", i); + if (is_end_point(i)) ret = ppc4xx_init_pcie_endport(i); - } else { - printf("PCIE%d: will be configured as root-complex\n", i); + else ret = ppc4xx_init_pcie_rootport(i); - } if (ret) { - printf("PCIE%d: initialization failed\n", i); + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } @@ -339,27 +338,27 @@ void pcie_setup_hoses(int busno) pci_register_hose(hose); if (is_end_point(i)) { - ppc4xx_setup_pcie_endpoint(hose, i); + ppc4xx_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. - */ + */ } else { - ppc4xx_setup_pcie_rootpoint(hose, i); + ppc4xx_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); if (delay > 5) - printf("Warning, expect noticable delay before " + printf("Warning, expect noticable delay before " "PCIe scan due to 'pciscandelay' value!\n"); mdelay(delay * 1000); } - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; } } }