X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Famcc%2Fkilauea%2Fkilauea.c;h=f30dc8f92411126fd5ae0abb2e22cd55d7ce5870;hb=794a5924972fc8073616e98a2668da4a5f9aea90;hp=2ee896abd9669c73fae73df27a6a6c18b71166ee;hpb=8d79953d03e6c5b24215609997dafe4daa623cd6;p=oweals%2Fu-boot.git

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 2ee896abd9..f30dc8f924 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -192,13 +192,6 @@ int board_early_init_f (void)
 	 */
 	mtsdr(SDR0_SRST, 0);
 
-	/*
-	 * Configure FPGA register with PCIe reset
-	 */
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc0);	/* assert PCIe reset */
-	mdelay(50);
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc3);	/* deassert PCIe reset */
-
 	/* Configure 405EX for NAND usage */
 	val = SDR0_CUST0_MUX_NDFC_SEL |
 		SDR0_CUST0_NDFC_ENABLE |
@@ -214,6 +207,13 @@ int board_early_init_f (void)
 	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
 	mtsdr(SDR0_PFC1, val);
 
+	/*
+	 * Configure FPGA register with PCIe reset
+	 */
+	out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
+	mdelay(50);
+	out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
+
 	return 0;
 }
 
@@ -230,14 +230,22 @@ int misc_init_r(void)
 	return 0;
 }
 
-int board_emac_count(void)
+static int is_405exr(void)
 {
 	u32 pvr = get_pvr();
 
+	if (pvr & 0x00000004)
+		return 0;		/* bit 2 set -> 405EX */
+
+	return 1;			/* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
 	/*
 	 * 405EXr only has one EMAC interface, 405EX has two
 	 */
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		return 1;
 	else
 		return 2;
@@ -245,12 +253,10 @@ int board_emac_count(void)
 
 static int board_pcie_count(void)
 {
-	u32 pvr = get_pvr();
-
 	/*
 	 * 405EXr only has one EMAC interface, 405EX has two
 	 */
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		return 1;
 	else
 		return 2;
@@ -259,9 +265,8 @@ static int board_pcie_count(void)
 int checkboard (void)
 {
 	char *s = getenv("serial#");
-	u32 pvr = get_pvr();
 
-	if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+	if (is_405exr())
 		printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
 	else
 		printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
@@ -333,27 +338,27 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 		if (is_end_point(i)) {
-		    	ppc4xx_setup_pcie_endpoint(hose, i);
+			ppc4xx_setup_pcie_endpoint(hose, i);
 			/*
 			 * Reson for no scanning is endpoint can not generate
 			 * upstream configuration accesses.
-		    	 */
+			 */
 		} else {
-		    	ppc4xx_setup_pcie_rootpoint(hose, i);
+			ppc4xx_setup_pcie_rootpoint(hose, i);
 			env = getenv ("pciscandelay");
-		    	if (env != NULL) {
-			    	delay = simple_strtoul(env, NULL, 10);
+			if (env != NULL) {
+				delay = simple_strtoul(env, NULL, 10);
 				if (delay > 5)
-				    	printf("Warning, expect noticable delay before "
+					printf("Warning, expect noticable delay before "
 					       "PCIe scan due to 'pciscandelay' value!\n");
 				mdelay(delay * 1000);
 			}
 
-		    	/*
-		     	 * Config access can only go down stream
-		     	 */
-		    	hose->last_busno = pci_hose_scan(hose);
-		    	bus = hose->last_busno + 1;
+			/*
+			 * Config access can only go down stream
+			 */
+			hose->last_busno = pci_hose_scan(hose);
+			bus = hose->last_busno + 1;
 		}
 	}
 }