X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Famcc%2Fkilauea%2Fkilauea.c;h=37ef06ef2a77648fd26c482ff2873afd9819a7f7;hb=e57ed96baca1222e6cd3d7032691a89d5890bb4a;hp=36e9e4a21171214886787d4e5e04a5e03b8cf9d4;hpb=e15e33433e7c05111968dc9b434a52fd42cbd221;p=oweals%2Fu-boot.git

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 36e9e4a211..37ef06ef2a 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -25,6 +25,7 @@
 #include <ppc4xx.h>
 #include <ppc405.h>
 #include <libfdt.h>
+#include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -191,13 +192,6 @@ int board_early_init_f (void)
 	 */
 	mtsdr(SDR0_SRST, 0);
 
-	/*
-	 * Configure FPGA register with PCIe reset
-	 */
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc0);	/* assert PCIe reset */
-	mdelay(50);
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc3);	/* deassert PCIe reset */
-
 	/* Configure 405EX for NAND usage */
 	val = SDR0_CUST0_MUX_NDFC_SEL |
 		SDR0_CUST0_NDFC_ENABLE |
@@ -206,6 +200,20 @@ int board_early_init_f (void)
 		(0x80000000 >> (28 + CFG_NAND_CS));
 	mtsdr(SDR0_CUST0, val);
 
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * -> Enable USB
+	 */
+	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+	mtsdr(SDR0_PFC1, val);
+
+	/*
+	 * Configure FPGA register with PCIe reset
+	 */
+	out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
+	mdelay(50);
+	out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
+
 	return 0;
 }