X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2Famcc%2Facadia%2Fmemory.c;h=703a6686ea2920606c19ee4e467ded8199492dbc;hb=fc1ff1971a20c83e9417ba30366086b3e2e97de6;hp=48a6725745614dbcf16d11e032d72da464fa2f5d;hpb=794a5924972fc8073616e98a2668da4a5f9aea90;p=oweals%2Fu-boot.git

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 48a6725745..703a6686ea 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -29,7 +29,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/gpio.h>
+#include <asm/ppc4xx-gpio.h>
 
 extern void board_pll_init_f(void);
 
@@ -39,7 +39,7 @@ static void cram_bcr_write(u32 wr_val)
 	wr_val <<= 2;
 
 	/* set CRAM_CRE to 1 */
-	gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
 
 	/* Write BCR to CRAM on CS1 */
 	out32(wr_val + 0x00200000, 0);
@@ -53,7 +53,7 @@ static void cram_bcr_write(u32 wr_val)
 	eieio();
 
 	/* set CRAM_CRE back to 0 (normal operation) */
-	gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
 
 	return;
 }
@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
 	u32 reg;
 
 	/* don't reinit PLL when booting via I2C bootstrap option */
-	mfsdr(SDR_PINSTP, reg);
+	mfsdr(SDR0_PINSTP, reg);
 	if (reg != 0xf0000000)
 		board_pll_init_f();
 #endif
@@ -75,36 +75,36 @@ phys_size_t initdram(int board_type)
 	u32 val;
 
 	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
-	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
 
 	/* 2. EBC in Async mode */
-	mtebc(pb1ap, 0x078F1EC0);
-	mtebc(pb2ap, 0x078F1EC0);
-	mtebc(pb1cr, 0x000BC000);
-	mtebc(pb2cr, 0x020BC000);
+	mtebc(PB1AP, 0x078F1EC0);
+	mtebc(PB2AP, 0x078F1EC0);
+	mtebc(PB1CR, 0x000BC000);
+	mtebc(PB2CR, 0x020BC000);
 
 	/* 3. Set CRAM in Sync mode */
 	cram_bcr_write(0x7012);		/* CRAM burst setting */
 
 	/* 4. EBC in Sync mode */
-	mtebc(pb1ap, 0x9C0201C0);
-	mtebc(pb2ap, 0x9C0201C0);
+	mtebc(PB1AP, 0x9C0201C0);
+	mtebc(PB2AP, 0x9C0201C0);
 
 	/* Set GPIO pins back to alternate function */
-	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
 
 	/* Config EBC to use RDY */
-	mfsdr(sdrultra0, val);
-	mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
+	mfsdr(SDR0_ULTRA0, val);
+	mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
 
 	/* Wait a short while, since for NAND booting this is too fast */
 	for (i=0; i<200000; i++)
 		;
 #endif
 
-	return (CFG_MBYTES_RAM << 20);
+	return (CONFIG_SYS_MBYTES_RAM << 20);
 }