X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=board%2FMigoR%2Flowlevel_init.S;h=e48f7b3b10b59a87e8c151dad608dd0e8e5a16a8;hb=9d2459f3532c009bb903b02b57079a3862420a5f;hp=7fd771d6937d5f2af630420d634c0bcb32079c40;hpb=5c395393cc9b85b14c5481dbcab6b67b54f31622;p=oweals%2Fu-boot.git

diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S
index 7fd771d693..e48f7b3b10 100644
--- a/board/MigoR/lowlevel_init.S
+++ b/board/MigoR/lowlevel_init.S
@@ -42,7 +42,6 @@
 	.align	2
 
 lowlevel_init:
-
 	mov.l	CCR_A, r1	! Address of Cache Control Register
 	mov.l	CCR_D, r0	! Instruction Cache Invalidate
 	mov.l	r0, @r1
@@ -88,7 +87,7 @@ lowlevel_init:
 	mov.w	r0, @r1
 
 	mov.l	DLLFRQ_A, r1	! 20080115
-	mov.l	DLLFRQ_D, r0 	! 20080115
+	mov.l	DLLFRQ_D, r0	! 20080115
 	mov.l	r0, @r1
 
 	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
@@ -100,13 +99,12 @@ lowlevel_init:
 	mov.l	r0, @r1
 
 bsc_init:
-
 	mov.l	CMNCR_A, r1	! CMNCR address -> R1
-	mov.l 	CMNCR_D, r0	! CMNCR data    -> R0
+	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
 	mov.l	r0, @r1		! CMNCR set
 
 	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
-	mov.l 	CS0BCR_D, r0	! CS0BCR data    -> R0
+	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
 	mov.l	r0, @r1		! CS0BCR set
 
 	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
@@ -114,35 +112,35 @@ bsc_init:
 	mov.l	r0, @r1		! CS4BCR set
 
 	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
-	mov.l 	CS5ABCR_D, r0	! CS5ABCR data    -> R0
+	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
 	mov.l	r0, @r1		! CS5ABCR set
 
 	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
-	mov.l 	CS5BBCR_D, r0	! CS5BBCR data    -> R0
+	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
 	mov.l	r0, @r1		! CS5BBCR set
 
 	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
-	mov.l 	CS6ABCR_D, r0	! CS6ABCR data    -> R0
+	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
 	mov.l	r0, @r1		! CS6ABCR set
 
 	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
-	mov.l 	CS0WCR_D, r0	! CS0WCR data    -> R0
+	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
 	mov.l	r0, @r1		! CS0WCR set
 
 	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
-	mov.l 	CS4WCR_D, r0	! CS4WCR data    -> R0
+	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
 	mov.l	r0, @r1		! CS4WCR set
 
 	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
-	mov.l 	CS5AWCR_D, r0	! CS5AWCR data    -> R0
+	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
 	mov.l	r0, @r1		! CS5AWCR set
 
 	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
-	mov.l 	CS5BWCR_D, r0	! CS5BWCR data    -> R0
+	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
 	mov.l	r0, @r1		! CS5BWCR set
 
 	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
-	mov.l 	CS6AWCR_D, r0	! CS6AWCR data    -> R0
+	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
 	mov.l	r0, @r1		! CS6AWCR set
 
 	! SDRAM initialization
@@ -175,7 +173,7 @@ bsc_init:
 	mov.l	r0, @r1
 
 	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
-	mov 	#0x00, r0	! SDMR3 data    -> R0
+	mov	#0x00, r0	! SDMR3 data    -> R0
 	mov.b	r0, @r1		! SDMR3 set
 
 	! BL bit off (init = ON)  (?!?)
@@ -188,8 +186,6 @@ bsc_init:
 	rts
 	mov	#0, r0
 
-
-
 	.align	4
 
 CCR_A:		.long	CCR
@@ -266,4 +262,3 @@ PSCR_D:		.word	0x0000
 RWTCSR_D_1:	.word	0xA507
 RWTCSR_D_2:	.word	0xA504		! 20080115
 RWTCNT_D:	.word	0x5A00
-