X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fx86%2Flib%2Fspl.c;h=cf22fa2d7b5f73801aa2401cdea185a6f9a74dc7;hb=c27178ba3649f539c9f1890ea147f4c5415f63b5;hp=7623fc9ada0777d585f25d6e2d2f7842a304b93a;hpb=6891152a4596d38ac25d2fe1238e3b6a938554b8;p=oweals%2Fu-boot.git diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 7623fc9ada..cf22fa2d7b 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -4,12 +4,22 @@ */ #include +#include #include +#include +#include +#include +#include +#include +#include #include #include +#include #include +#include #include #include +#include #include #include #include @@ -21,6 +31,32 @@ __weak int arch_cpu_init_dm(void) return 0; } +#ifdef CONFIG_TPL + +static int set_max_freq(void) +{ + if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) { + /* + * Burst Mode has been factory-configured as disabled and is not + * available in this physical processor package + */ + debug("Burst Mode is factory-disabled\n"); + return -ENOENT; + } + + /* Enable burst mode */ + cpu_set_burst_mode(true); + + /* Enable speed step */ + cpu_set_eist(true); + + /* Set P-State ratio */ + cpu_set_p_state_to_turbo_ratio(); + + return 0; +} +#endif + static int x86_spl_init(void) { #ifndef CONFIG_TPL @@ -30,11 +66,17 @@ static int x86_spl_init(void) * is not needed. We could make this a CONFIG option or perhaps * place it immediately below CONFIG_SYS_TEXT_BASE. */ - char *ptr = (char *)0x110000; + __maybe_unused char *ptr = (char *)0x110000; +#else + struct udevice *punit; #endif int ret; debug("%s starting\n", __func__); + if (IS_ENABLED(TPL)) + ret = x86_cpu_reinit_f(); + else + ret = x86_cpu_init_f(); ret = spl_init(); if (ret) { debug("%s: spl_init() failed\n", __func__); @@ -72,7 +114,8 @@ static int x86_spl_init(void) __func__, ret); } -#ifndef CONFIG_TPL +#ifndef CONFIG_SYS_COREBOOT +# ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ @@ -101,6 +144,15 @@ static int x86_spl_init(void) return ret; } mtrr_commit(true); +# else + ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); + if (ret) + debug("Could not find PUNIT (err=%d)\n", ret); + + ret = set_max_freq(); + if (ret) + debug("Failed to set CPU frequency (err=%d)\n", ret); +# endif #endif return 0; @@ -112,10 +164,10 @@ void board_init_f(ulong flags) ret = x86_spl_init(); if (ret) { - debug("Error %d\n", ret); - panic("x86_spl_init fail"); + printf("x86_spl_init: error %d\n", ret); + hang(); } -#ifdef CONFIG_TPL +#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT) gd->bd = malloc(sizeof(*gd->bd)); if (!gd->bd) { printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd)); @@ -160,6 +212,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image, spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; + if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) { + /* + * Copy U-Boot from ROM + * TODO(sjg@chromium.org): Figure out a way to get the text base + * correctly here, and in the device-tree binman definition. + * + * Also consider using FIT so we get the correct image length + * and parameters. + */ + memcpy((char *)spl_image->load_addr, (char *)0xfff00000, + 0x100000); + } + debug("Loading to %lx\n", spl_image->load_addr); return 0;