X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fx86%2Fcpu%2Fpci.c;h=c209f15ec4a8787364080467fffed562eda65cc1;hb=8c38e4d0b8d37dcd3bfd2293481e220b1b4a3a42;hp=ab1aaaa0599e0e195f910fd3c27e2fe3c28b9b6f;hpb=306df2c8241bd363c71a99841630fb5e85d81fae;p=oweals%2Fu-boot.git

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index ab1aaaa059..c209f15ec4 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -10,9 +10,11 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -70,7 +72,7 @@ static struct pci_controller *get_hose(void)
 	return pci_bus_to_hose(0);
 }
 
-unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
 {
 	uint8_t value;
 
@@ -79,7 +81,7 @@ unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
 {
 	uint16_t value;
 
@@ -88,7 +90,7 @@ unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
 {
 	uint32_t value;
 
@@ -97,17 +99,76 @@ unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_byte(get_hose(), dev, where, value);
 }
 
-void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_word(get_hose(), dev, where, value);
 }
 
-void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_dword(get_hose(), dev, where, value);
 }
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			ulong *valuep, enum pci_size_t size)
+{
+	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = inb(PCI_REG_DATA + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		*valuep = inw(PCI_REG_DATA + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		*valuep = inl(PCI_REG_DATA);
+		break;
+	}
+
+	return 0;
+}
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			 ulong value, enum pci_size_t size)
+{
+	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		outb(value, PCI_REG_DATA + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		outw(value, PCI_REG_DATA + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		outl(value, PCI_REG_DATA);
+		break;
+	}
+
+	return 0;
+}
+
+void pci_assign_irqs(int bus, int device, int func, u8 irq[4])
+{
+	pci_dev_t bdf;
+	u8 pin, line;
+
+	bdf = PCI_BDF(bus, device, func);
+
+	pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+
+	/* PCI spec says all values except 1..4 are reserved */
+	if ((pin < 1) || (pin > 4))
+		return;
+
+	line = irq[pin - 1];
+
+	debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
+	      line, bus, device, func, 'A' + pin - 1);
+
+	x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+}