X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fx86%2FKconfig;h=5c23b2cb57f1dd46e6c2a76c5c5deb53a3a56aed;hb=6ea51d286093aa21619cc2a55263caf1e9d5f340;hp=277c3babf37495623730d8a03e64ca0635a4172c;hpb=2ddb1a177ada3b9edd327fe7e74e4891e462a6f0;p=oweals%2Fu-boot.git

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 277c3babf3..5c23b2cb57 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -108,6 +108,7 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
 source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
@@ -151,6 +152,7 @@ config SMM_TSEG_SIZE
 config X86_RESET_VECTOR
 	bool
 	default n
+	select BINMAN
 
 # The following options control where the 16-bit and 32-bit init lies
 # If SPL is enabled then it normally holds this init code, and U-Boot proper
@@ -401,15 +403,6 @@ config FSP_BROKEN_HOB
 	  do not overwrite the important boot service data which is used by
 	  FSP, otherwise the subsequent call to fsp_notify() will fail.
 
-config FSP_LOCKDOWN_SPI
-	bool
-	depends on HAVE_FSP
-	help
-	  Some Intel FSP (like Braswell) does SPI lock-down during the call
-	  to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
-	  for such FSP and U-Boot will configure the SPI opcode registers
-	  before the lock-down.
-
 config ENABLE_MRC_CACHE
 	bool "Enable MRC cache"
 	depends on !EFI && !SYS_COREBOOT
@@ -558,6 +551,48 @@ config VGA_BIOS_ADDR
 	  address of 0xfff90000 indicates that the image will be put at offset
 	  0x90000 from the beginning of a 1MB flash device.
 
+config HAVE_VBT
+	bool "Add a Video BIOS Table (VBT) image"
+	depends on HAVE_FSP
+	help
+	  Select this option if you have a Video BIOS Table (VBT) image that
+	  you would like to add to your ROM. This is normally required if you
+	  are using an Intel FSP firmware that is complaint with spec 1.1 or
+	  later to initialize the integrated graphics device (IGD).
+
+	  Video BIOS Table, or VBT, provides platform and board specific
+	  configuration information to the driver that is not discoverable
+	  or available through other means. By other means the most used
+	  method here is to read EDID table from the attached monitor, over
+	  Display Data Channel (DDC) using two pin I2C serial interface. VBT
+	  configuration is related to display hardware and is available via
+	  the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+	string "Video BIOS Table (VBT) image filename"
+	depends on HAVE_VBT
+	default "vbt.bin"
+	help
+	  The filename of the file to use as Video BIOS Table (VBT) image
+	  in the board directory.
+
+config VBT_ADDR
+	hex "Video BIOS Table (VBT) image location"
+	depends on HAVE_VBT
+	default 0xfff90000
+	help
+	  The location of Video BIOS Table (VBT) image in the SPI flash. For
+	  example, base address of 0xfff90000 indicates that the image will
+	  be put at offset 0x90000 from the beginning of a 1MB flash device.
+
+config VIDEO_FSP
+	bool "Enable FSP framebuffer driver support"
+	depends on HAVE_VBT && DM_VIDEO
+	help
+	  Turn on this option to enable a framebuffer driver when U-Boot is
+	  using Video BIOS Table (VBT) image for FSP firmware to initialize
+	  the integrated graphics device.
+
 config ROM_TABLE_ADDR
 	hex
 	default 0xf0000
@@ -621,6 +656,7 @@ endmenu
 
 config HAVE_ACPI_RESUME
 	bool "Enable ACPI S3 resume"
+	select ENABLE_MRC_CACHE
 	help
 	  Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
 	  state where all system context is lost except system memory. U-Boot
@@ -634,7 +670,6 @@ config HAVE_ACPI_RESUME
 config S3_VGA_ROM_RUN
 	bool "Re-run VGA option ROMs on S3 resume"
 	depends on HAVE_ACPI_RESUME
-	default y if HAVE_ACPI_RESUME
 	help
 	  Execute VGA option ROMs in U-Boot when resuming from S3. Normally
 	  this is needed when graphics console is being used in the kernel.