X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fx86%2FKconfig;h=1d08cb24fb5bcca9838ed46d15397ebd31d971d7;hb=8bd5dcd89581018f163e3424c8d2a3268ca79544;hp=e0520937751076aa3971153ceb242f2ad6290938;hpb=8bf3c2442b59aedd1e58b7013fc12180cab0b541;p=oweals%2Fu-boot.git diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e052093775..1d08cb24fb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,7 +32,6 @@ config X86_RUN_32BIT config X86_RUN_64BIT bool "64-bit" select X86_64 - select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS help @@ -116,6 +115,7 @@ source "arch/x86/cpu/efi/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/slimbootloader/Kconfig" source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below @@ -177,10 +177,17 @@ config X86_16BIT_INIT config SPL_X86_16BIT_INIT bool depends on X86_RESET_VECTOR - default y if X86_RESET_VECTOR && SPL + default y if X86_RESET_VECTOR && SPL && !TPL help This is enabled when 16-bit init is in SPL +config TPL_X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && TPL + help + This is enabled when 16-bit init is in TPL + config X86_32BIT_INIT bool depends on X86_RESET_VECTOR @@ -200,11 +207,6 @@ config RESET_SEG_START depends on X86_RESET_VECTOR default 0xffff0000 -config RESET_SEG_SIZE - hex - depends on X86_RESET_VECTOR - default 0x10000 - config RESET_VEC_LOC hex depends on X86_RESET_VECTOR @@ -215,6 +217,14 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 +config HAVE_X86_FIT + bool + help + Enable inclusion of an Intel Firmware Interface Table (FIT) into the + image. This table is supposed to point to microcode and the like. So + far it is just a fixed table with the minimum set of headers, so that + it is actually present. + config X86_LOAD_FROM_32_BIT bool "Boot from a 32-bit program" help @@ -324,7 +334,7 @@ config X86_RAMTEST config FLASH_DESCRIPTOR_FILE string "Flash descriptor binary filename" - depends on HAVE_INTEL_ME + depends on HAVE_INTEL_ME || FSP_VERSION2 default "descriptor.bin" help The filename of the file to use as flash descriptor in the @@ -338,9 +348,17 @@ config INTEL_ME_FILE The filename of the file to use as Intel Management Engine in the board directory. +config USE_HOB + bool "Use HOB (Hand-Off Block)" + help + Select this option to access HOB (Hand-Off Block) data structures + and parse HOBs. This HOB infra structure can be reused with + different solutions across different platforms. + config HAVE_FSP bool "Add an Firmware Support Package binary" depends on !EFI + select USE_HOB help Select this option to add an Firmware Support Package binary to the resulting U-Boot image. It is a binary blob which U-Boot uses @@ -349,9 +367,40 @@ config HAVE_FSP Note: Without this binary U-Boot will not be able to set up its SDRAM so will not boot. +config USE_CAR + bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up" + default y if !HAVE_FSP + help + Select this option if your board uses CAR init code, typically in a + car.S file, to get some initial memory for code execution. This is + common with Intel CPUs which don't use FSP. + +choice + prompt "FSP version" + depends on HAVE_FSP + default FSP_VERSION1 + help + Selects the FSP version to use. Intel has published several versions + of the FSP External Architecture Specification and this allows + selection of the version number used by a particular SoC. + +config FSP_VERSION1 + bool "FSP version 1.x" + help + This covers versions 1.0 and 1.1a. See here for details: + https://github.com/IntelFsp/fsp/wiki + +config FSP_VERSION2 + bool "FSP version 2.x" + help + This covers versions 2.0 and 2.1. See here for details: + https://github.com/IntelFsp/fsp/wiki + +endchoice + config FSP_FILE string "Firmware Support Package binary filename" - depends on HAVE_FSP + depends on FSP_VERSION1 default "fsp.bin" help The filename of the file to use as Firmware Support Package binary @@ -359,7 +408,7 @@ config FSP_FILE config FSP_ADDR hex "Firmware Support Package binary location" - depends on HAVE_FSP + depends on FSP_VERSION1 default 0xfffc0000 help FSP is not Position Independent Code (PIC) and the whole FSP has to @@ -370,9 +419,57 @@ config FSP_ADDR The default base address of 0xfffc0000 indicates that the binary must be located at offset 0xc0000 from the beginning of a 1MB flash device. +if FSP_VERSION2 + +config FSP_FILE_T + string "Firmware Support Package binary filename (Temp RAM)" + default "fsp_t.bin" + help + The filename of the file to use for the temporary-RAM init phase from + the Firmware Support Package binary. Put this in the board directory. + It is used to set up an initial area of RAM which can be used for the + stack and other purposes, while bringing up the main system DRAM. + +config FSP_ADDR_T + hex "Firmware Support Package binary location (Temp RAM)" + default 0xffff8000 + help + FSP is not Position-Independent Code (PIC) and FSP components have to + be rebased if placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + +config FSP_FILE_M + string "Firmware Support Package binary filename (Memory Init)" + default "fsp_m.bin" + help + The filename of the file to use for the RAM init phase from the + Firmware Support Package binary. Put this in the board directory. + It is used to set up the main system DRAM and runs in SPL, once + temporary RAM (CAR) is working. + +config FSP_FILE_S + string "Firmware Support Package binary filename (Silicon Init)" + default "fsp_s.bin" + help + The filename of the file to use for the Silicon init phase from the + Firmware Support Package binary. Put this in the board directory. + It is used to set up the silicon to work correctly and must be + executed after DRAM is running. + +config IFWI_INPUT_FILE + string "Filename containing FIT (Firmware Interface Table) with IFWI" + default "fitimage.bin" + help + The IFWI is obtained by running a tool on this file to extract the + IFWI. Put this in the board directory. The IFWI contains U-Boot TPL, + microcode and other internal items. + +endif + config FSP_TEMP_RAM_ADDR hex - depends on HAVE_FSP + depends on FSP_VERSION1 default 0x2000000 help Stack top address which is used in fsp_init() after DRAM is ready and @@ -380,14 +477,14 @@ config FSP_TEMP_RAM_ADDR config FSP_SYS_MALLOC_F_LEN hex - depends on HAVE_FSP + depends on FSP_VERSION1 default 0x100000 help Additional size of malloc() pool before relocation. config FSP_USE_UPD bool - depends on HAVE_FSP + depends on FSP_VERSION1 default y help Most FSPs use UPD data region for some FSP customization. But there @@ -396,7 +493,7 @@ config FSP_USE_UPD config FSP_BROKEN_HOB bool - depends on HAVE_FSP + depends on FSP_VERSION1 help Indicate some buggy FSPs that does not report memory used by FSP itself as reserved in the resource descriptor HOB. Select this to @@ -414,8 +511,8 @@ config ENABLE_MRC_CACHE For platforms that use Intel FSP for the memory initialization, please check FSP output HOB via U-Boot command 'fsp hob' to see - if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). - If such GUID does not exist, MRC cache is not avaiable on such + if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h). + If such GUID does not exist, MRC cache is not available on such platform (eg: Intel Queensbay), which means selecting this option here does not make any difference. @@ -491,6 +588,10 @@ config HAVE_REFCODE broadwell) U-Boot will be missing some critical setup steps. Various peripherals may fail to work. +config HAVE_MICROCODE + bool + default y if !FSP_VERSION2 + config SMP bool "Enable Symmetric Multiprocessing" default n @@ -782,4 +883,30 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config INTEL_CAR_CQOS + bool "Support Intel Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up a portion of L2 cache for + CAR and use the remainder for actual caching. + +# +# Each bit in QOS mask controls this many bytes. This is calculated as: +# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS +# +config CACHE_QOS_SIZE_PER_BIT + hex + depends on INTEL_CAR_CQOS + default 0x20000 # 128 KB + +config X86_OFFSET_U_BOOT + hex "Offset of U-Boot in ROM image" + depends on HAVE_SYS_TEXT_BASE + default SYS_TEXT_BASE + +config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on SPL && X86 + default SPL_TEXT_BASE + endmenu