X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fprocessor.h;h=2ed51b12486b62f3cbe535eb386a3396328d5ee1;hb=acc2372db020b9415142e93a1c30f57c1d3aa5c2;hp=a5e7a612bfd136b718af6cf83e4b28918ef47abe;hpb=3fe1a8545b55d31a6db2d9e60d962c4f6e048913;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index a5e7a612bf..2ed51b1248 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -378,11 +378,16 @@
 #else
 #define SPRN_TCR	0x154	/* Book E Timer Control Register */
 #endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define  TCR_WP(x)		(((64-x)&0x3)<<30)| \
+				(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
 #define   TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
 #define     WP_2_17		0		/* 2^17 clocks */
 #define     WP_2_21		1		/* 2^21 clocks */
 #define     WP_2_25		2		/* 2^25 clocks */
 #define     WP_2_29		3		/* 2^29 clocks */
+#endif /* CONFIG_E500 */
 #define   TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
 #define     WRC_NONE		0		/* No reset will occur */
 #define     WRC_CORE		1		/* Core reset will occur */
@@ -1118,7 +1123,6 @@
 #define SVR_B4860	0X868000
 #define SVR_G4860	0x868001
 #define SVR_B4460	0x868003
-#define SVR_G4060	0x868003
 #define SVR_B4440	0x868100
 #define SVR_G4440	0x868101
 #define SVR_B4420	0x868102
@@ -1129,6 +1133,10 @@
 #define SVR_T1020	0x852100
 #define SVR_T1021	0x852101
 #define SVR_T1022	0x852102
+#define SVR_T1024	0x854000
+#define SVR_T1023	0x854100
+#define SVR_T1014	0x854400
+#define SVR_T1013	0x854500
 #define SVR_T2080	0x853000
 #define SVR_T2081	0x853100