X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Ffsl_secure_boot.h;h=64c10074a896d2dd2001ee10826d17d25915c0bd;hb=e8f80a5a58c9b506453cc0780687e8ed457d30a6;hp=2e937f0364b9503dc758e52a7e7950a789a10306;hpb=69d4b48c84b9c2b762066c5a68406a53e49ea2f3;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 2e937f0364..64c10074a8 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __FSL_SECURE_BOOT_H
@@ -9,32 +8,31 @@
 #include <asm/config_mpc85xx.h>
 
 #ifdef CONFIG_SECURE_BOOT
-
-#ifndef CONFIG_FIT_SIGNATURE
-#define CONFIG_CHAIN_OF_TRUST
-#endif
-
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
 #else
 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
 #endif
 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
-#if defined(CONFIG_B4860QDS) || \
-	defined(CONFIG_T4240QDS) || \
-	defined(CONFIG_T2080QDS) || \
-	defined(CONFIG_T2080RDB) || \
-	defined(CONFIG_T1040QDS) || \
-	defined(CONFIG_T104xD4QDS) || \
-	defined(CONFIG_T104xRDB) || \
-	defined(CONFIG_T104xD4RDB) || \
-	defined(CONFIG_PPC_T1023) || \
-	defined(CONFIG_PPC_T1024)
+#if defined(CONFIG_TARGET_B4860QDS) || \
+	defined(CONFIG_TARGET_B4420QDS) || \
+	defined(CONFIG_TARGET_T4160QDS) || \
+	defined(CONFIG_TARGET_T4240QDS) || \
+	defined(CONFIG_TARGET_T2080QDS) || \
+	defined(CONFIG_TARGET_T2080RDB) || \
+	defined(CONFIG_TARGET_T1040QDS) || \
+	defined(CONFIG_TARGET_T1040RDB) || \
+	defined(CONFIG_TARGET_T1040D4RDB) || \
+	defined(CONFIG_TARGET_T1042RDB) || \
+	defined(CONFIG_TARGET_T1042D4RDB) || \
+	defined(CONFIG_TARGET_T1042RDB_PI) || \
+	defined(CONFIG_ARCH_T1023) || \
+	defined(CONFIG_ARCH_T1024)
 #ifndef CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_CPC_REINIT_F
 #endif
@@ -54,15 +52,15 @@
 #endif
 #endif
 
-#if defined(CONFIG_C29XPCIE)
+#if defined(CONFIG_TARGET_C29XPCIE)
 #define CONFIG_KEY_REVOCATION
 #endif
 
-#if defined(CONFIG_PPC_P3041)	||	\
-	defined(CONFIG_PPC_P4080) ||	\
-	defined(CONFIG_PPC_P5020) ||	\
-	defined(CONFIG_PPC_P5040) ||	\
-	defined(CONFIG_PPC_P2041)
+#if defined(CONFIG_ARCH_P3041)	||	\
+	defined(CONFIG_ARCH_P4080) ||	\
+	defined(CONFIG_ARCH_P5020) ||	\
+	defined(CONFIG_ARCH_P5040) ||	\
+	defined(CONFIG_ARCH_P2041)
 	#define	CONFIG_FSL_TRUST_ARCH_v1
 #endif
 
@@ -79,13 +77,7 @@
 #endif /* #ifdef CONFIG_SECURE_BOOT */
 
 #ifdef CONFIG_CHAIN_OF_TRUST
-
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DM			1
-#define CONFIG_SPL_CRYPTO_SUPPORT
-#define CONFIG_SPL_HASH_SUPPORT
-#define CONFIG_SPL_RSA
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 /*
  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  * due to space crunch on CPC and thus malloc will not work.
@@ -106,24 +98,13 @@
 #define CONFIG_SPL_UBOOT_KEY_HASH	NULL
 #endif /* ifdef CONFIG_SPL_BUILD */
 
-#define CONFIG_CMD_ESBC_VALIDATE
-#define CONFIG_CMD_BLOB
 #define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA_FREESCALE_EXP
-
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
 
 #ifndef CONFIG_SPL_BUILD
 /*
  * fsl_setenv_chain_of_trust() must be called from
  * board_late_init()
  */
-#ifndef CONFIG_BOARD_LATE_INIT
-#define CONFIG_BOARD_LATE_INIT
-#endif
 
 /* If Boot Script is not on NOR and is required to be copied on RAM */
 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
@@ -140,13 +121,13 @@
 /* The bootscript header address is different for B4860 because the NOR
  * mapping is different on B4 due to reduced NOR size.
  */
-#if defined(CONFIG_B4860QDS)
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
 #elif defined(CONFIG_FSL_CORENET)
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
 #else
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000