X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Finclude%2Fasm%2Fcache.h;h=5f9c640aa2aff83a4d43cb1a62e1d65b464b7075;hb=31043e20ae748635f142483e8b7b645948687055;hp=53e8d05f50b1a251484e8be719ab216350e1c6b5;hpb=a47a12becf66f02a56da91c161e2edb625e9f20c;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 53e8d05f50..5f9c640aa2 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -8,7 +8,7 @@
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
 #define	L1_CACHE_SHIFT	4
 #elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
@@ -20,6 +20,12 @@
 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
 /*
  * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  */