X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fppc4xx%2Fmiiphy.c;h=10147de0897d7be956e014ce120759fe55144af3;hb=d77fa2ff766bbb4b867e791187f78b6033071613;hp=3b28122014e6f83203ce9dd67f68e1dbf9315168;hpb=b36df561154bdd0a41bb77e09c5575ca2cf48013;p=oweals%2Fu-boot.git diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 3b28122014..10147de089 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -1,25 +1,6 @@ -/*-----------------------------------------------------------------------------+ - | This source code is dual-licensed. You may use it under the terms of the - | GNU General Public License version 2, or under the license below. - | - | This source code has been made available to you by IBM on an AS-IS - | basis. Anyone receiving this source is licensed under IBM - | copyrights to use it in any way he or she deems fit, including - | copying it, modifying it, compiling it, and redistributing it either - | with or without modifications. No license under IBM patents or - | patent applications is to be implied by the copyright license. - | - | Any user of this software should understand that IBM cannot provide - | technical support for this software and will not be responsible for - | any consequences resulting from the use of this software. - | - | Any person who transfers this source code or any derivative work - | must include the IBM copyright notice, this paragraph, and the - | preceding two paragraphs in the transferred software. - | - | COPYRIGHT I B M CORPORATION 1995 - | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - +-----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ /*-----------------------------------------------------------------------------+ | | File Name: miiphy.c @@ -89,60 +70,60 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 exsr = 0x0000; #endif - miiphy_read (devname, addr, PHY_BMSR, &bmsr); + miiphy_read (devname, addr, MII_BMSR, &bmsr); #if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); + if (bmsr & BMSR_ESTATEN) + miiphy_read (devname, addr, MII_ESTATUS, &exsr); - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { /* 1000BASE-X */ u16 anar = 0x0000; - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; + if (exsr & ESTATUS_1000XF) + anar |= ADVERTISE_1000XFULL; - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; + if (exsr & ESTATUS_1000XH) + anar |= ADVERTISE_1000XHALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); } else #endif { u16 anar, btcr; - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + miiphy_read (devname, addr, MII_ADVERTISE, &anar); + anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | + LPA_100HALF | LPA_10FULL | LPA_10HALF); - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + miiphy_read (devname, addr, MII_CTRL1000, &btcr); btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; + if (bmsr & BMSR_100BASE4) + anar |= LPA_100BASE4; - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; + if (bmsr & BMSR_100FULL) + anar |= LPA_100FULL; - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; + if (bmsr & BMSR_100HALF) + anar |= LPA_100HALF; - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; + if (bmsr & BMSR_10FULL) + anar |= LPA_10FULL; - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; + if (bmsr & BMSR_10HALF) + anar |= LPA_10HALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); #if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) + if (exsr & ESTATUS_1000_TFULL) btcr |= PHY_1000BTCR_1000FD; - if (exsr & PHY_EXSR_1000TH) + if (exsr & ESTATUS_1000_THALF) btcr |= PHY_1000BTCR_1000HD; - miiphy_write (devname, addr, PHY_1000BTCR, btcr); + miiphy_write (devname, addr, MII_CTRL1000, btcr); #endif } @@ -152,21 +133,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ u16 adv; - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | + LPA_10FULL | LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, MII_BMCR, &bmcr); + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, bmcr); return 0; } @@ -187,10 +168,9 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ unsigned int miiphy_getemac_offset(u8 addr) { -#if (defined(CONFIG_440) && \ +#if defined(CONFIG_440) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \ - defined(CONFIG_NET_MULTI) + !defined(CONFIG_460EX) && !defined(CONFIG_460GT) unsigned long zmii; unsigned long eoffset; @@ -228,7 +208,7 @@ unsigned int miiphy_getemac_offset(u8 addr) return (eoffset); #else -#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX) +#if defined(CONFIG_405EX) unsigned long rgmii; int devnum = 1;