X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fu-boot-nand_spl.lds;h=f04456442cb7c7cb105455460e882e160cf3e414;hb=bfebc8c965e41d62dc6355d09bdd63ca57011b99;hp=8410bd797933a16662e2574a487e1b33cf1ab046;hpb=c04bf5e9a45d7335681352faa125193258f8e976;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 8410bd7979..f04456442c 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -4,25 +4,11 @@
  *
  * Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include "config.h"
+
 OUTPUT_ARCH(powerpc)
 SECTIONS
 {
@@ -35,10 +21,11 @@ SECTIONS
 	.reloc : {
 		_GOT2_TABLE_ = .;
 		KEEP(*(.got2))
+		KEEP(*(.got))
 		_FIXUP_TABLE_ = .;
 		KEEP(*(.fixup))
 	}
-	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
 	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
 	. = ALIGN(8);
@@ -49,11 +36,25 @@ SECTIONS
 	}
 	_edata  =  .;
 
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
-
-	.resetvec ADDR(.text) + 0xffc : {
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+	.bootpg ADDR(.text) + 0x1000 :
+	{
+		start.o	(.bootpg)
+	}
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
 
@@ -62,6 +63,6 @@ SECTIONS
 		*(.sbss*)
 		*(.bss*)
 	}
-	__bss_end__ = .;
+	__bss_end = .;
 }
-ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
+ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");