X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Ft2080_serdes.c;h=fc63fe3613cc934bb7240f4e8c154f8dd9ce4c48;hb=d024236e5a31a2b4b82cbcc98b31b8170fc88d28;hp=f2fbdebec16e380d3bf542a6db56c40bb36efb7c;hpb=19210ae9838a867ce0243c41eafe928317c15b10;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index f2fbdebec1..fc63fe3613 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -43,7 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
-#if defined(CONFIG_PPC_T2080)
+	{0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -60,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, SGMII_FM1_DTSEC4,
@@ -116,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -128,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#elif defined(CONFIG_PPC_T2081)
 	{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
 	{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -138,11 +158,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
 	{}
 };
 
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
 static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
 	{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@@ -150,7 +169,9 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 	{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE,  NONE,  SATA1, SATA2} },
 	{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
 	{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
@@ -160,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 
 static const struct serdes_config *serdes_cfg_tbl[] = {
 	serdes1_cfg_tbl,
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
 	serdes2_cfg_tbl,
 #endif
 };