X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fspeed.c;h=cb8281e19e13e15204cfe6fb129149308207a342;hb=9925f1dbc38c0ef7220c6fca5968c708b8e48764;hp=35867dffdd718740184933d86456212e7fc1d09e;hpb=4641c211f6e37454c30770521c4de79c725036b0;p=oweals%2Fu-boot.git diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 35867dffdd..cb8281e19e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -27,16 +27,17 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(sys_info_t *sys_info) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; - u32 ccr; -#endif #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; +#ifdef CONFIG_HETROGENOUS_CLUSTERS + unsigned int dsp_cpu; + uint rcw_tmp1, rcw_tmp2; +#endif #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; #endif + __maybe_unused u32 svr; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -68,34 +69,40 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \ + defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; -#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK - uint single_src; -#endif sys_info->freq_systembus = sysclk; #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + /* * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS * are driven by separate DDR Refclock or single source * differential clock. */ - single_src = (in_be32(&gur->rcwsr[5]) >> + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; /* - * For single source clocking, both ddrclock and syclock + * For single source clocking, both ddrclock and sysclock * are driven by differential sysclock. */ - if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { - printf("Single Source Clock Configuration\n"); + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; - } else + else #endif #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; @@ -107,13 +114,37 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. + * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) - if (SVR_MAJ(get_svr()) >= 2) - mem_pll_rat *= 2; +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) + svr = get_svr(); + switch (SVR_SOC_VER(svr)) { + case SVR_T4240: + case SVR_T4160: + case SVR_T4120: + case SVR_T4080: + if (SVR_MAJ(svr) >= 2) + mem_pll_rat *= 2; + break; + case SVR_T2080: + case SVR_T2081: + if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) + mem_pll_rat *= 2; + break; + default: + break; + } #endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; @@ -127,6 +158,7 @@ void get_sys_info(sys_info_t *sys_info) else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } + #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * As per CHASSIS2 architeture total 12 clusters are posible and @@ -151,9 +183,27 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) + +#ifdef CONFIG_HETROGENOUS_CLUSTERS + for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) { + int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu); + u32 c_pll_sel = (in_be32 + (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + cplx_pll += cc_group[dsp_cluster] - 1; + sys_info->freq_processor_dsp[dsp_cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } +#endif + +#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ + defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) +#define FM1_CLK_SEL 0x00000007 +#define FM1_CLK_SHIFT 0 #else #define PME_CLK_SEL 0xe0000000 #define PME_CLK_SHIFT 29 @@ -161,8 +211,12 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SHIFT 26 #endif #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) + rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; +#else rcw_tmp = in_be32(&gur->rcwsr[7]); #endif +#endif #ifdef CONFIG_SYS_DPAA_PME #ifndef CONFIG_PME_PLAT_CLK_DIV @@ -199,7 +253,131 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sys_info->freq_qman = sys_info->freq_systembus / 2; +#ifndef CONFIG_QBMAN_CLK_DIV +#define CONFIG_QBMAN_CLK_DIV 2 +#endif + sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; +#endif + +#if defined(CONFIG_SYS_MAPLE) +#define CPRI_CLK_SEL 0x1C000000 +#define CPRI_CLK_SHIFT 26 +#define CPRI_ALT_CLK_SEL 0x00007000 +#define CPRI_ALT_CLK_SHIFT 12 + + rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ + rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ + /* For MAPLE and CPRI frequency */ + switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) { + case 1: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK]; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK]; + break; + case 2: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2; + break; + case 3: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3; + break; + case 4: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4; + break; + case 5: + if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) + >> CPRI_ALT_CLK_SHIFT) == 6) { + sys_info->freq_maple = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; + sys_info->freq_cpri = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2; + } + if (((rcw_tmp2 & CPRI_ALT_CLK_SEL) + >> CPRI_ALT_CLK_SHIFT) == 7) { + sys_info->freq_maple = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; + sys_info->freq_cpri = + freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3; + } + break; + case 6: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2; + break; + case 7: + sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; + sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3; + break; + default: + printf("Error: Unknown MAPLE/CPRI clock select!\n"); + } + + /* For MAPLE ULB and eTVPE frequencies */ +#define ULB_CLK_SEL 0x00000038 +#define ULB_CLK_SHIFT 3 +#define ETVPE_CLK_SEL 0x00000007 +#define ETVPE_CLK_SHIFT 0 + + switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) { + case 1: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK]; + break; + case 2: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2; + break; + case 3: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3; + break; + case 4: + sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4; + break; + case 5: + sys_info->freq_maple_ulb = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_maple_ulb = + freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2; + break; + case 7: + sys_info->freq_maple_ulb = + freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3; + break; + default: + printf("Error: Unknown MAPLE ULB clock select!\n"); + } + + switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) { + case 1: + sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK]; + break; + case 2: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2; + break; + case 3: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3; + break; + case 4: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4; + break; + case 5: + sys_info->freq_maple_etvpe = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2; + break; + case 7: + sys_info->freq_maple_etvpe = + freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3; + break; + default: + printf("Error: Unknown MAPLE eTVPE clock select!\n"); + } + #endif #ifdef CONFIG_SYS_DPAA_FMAN @@ -272,6 +450,48 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_ARCH_T2080) +#define ESDHC_CLK_SEL 0x00000007 +#define ESDHC_CLK_SHIFT 0 +#define ESDHC_CLK_RCWSR 15 +#else /* Support T1040 T1024 by now */ +#define ESDHC_CLK_SEL 0xe0000000 +#define ESDHC_CLK_SHIFT 29 +#define ESDHC_CLK_RCWSR 7 +#endif + rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); + switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) { + case 1: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK]; + break; + case 2: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2; + break; + case 3: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3; + break; +#if defined(CONFIG_SYS_SDHC_CLK_2_PLL) + case 4: + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4; + break; +#if defined(CONFIG_ARCH_T2080) + case 5: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK]; + break; +#endif + case 6: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2; + break; + case 7: + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3; + break; +#endif + default: + sys_info->freq_sdhc = 0; + printf("Error: Unknown SDHC peripheral clock select!\n"); + } +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { @@ -335,6 +555,10 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + #else /* CONFIG_FSL_CORENET */ uint plat_ratio, e500_ratio, half_freq_systembus; int i; @@ -367,7 +591,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_QE -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) sys_info->freq_qe = sys_info->freq_systembus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -383,39 +607,13 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_FSL_CORENET */ #if defined(CONFIG_FSL_LBC) - uint lcrr_div; -#if defined(CONFIG_SYS_LBC_LCRR) - /* We will program LCRR to this value later */ - lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; -#else - lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; -#endif - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if defined(CONFIG_FSL_CORENET) - /* If this is corenet based SoC, bit-representation - * for four times the clock divider values. - */ - lcrr_div *= 4; -#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ - !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider values. - */ - lcrr_div *= 2; -#endif - sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; - } else { - /* In case anyone cares what the unknown value is */ - sys_info->freq_localbus = lcrr_div; - } + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_LBC_CLK_DIV; #endif #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_IFC_CLK_DIV; #endif } @@ -423,7 +621,7 @@ void get_sys_info(sys_info_t *sys_info) int get_clocks (void) { sys_info_t sys_info; -#ifdef CONFIG_MPC8544 +#ifdef CONFIG_ARCH_MPC8544 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; #endif #if defined(CONFIG_CPM2) @@ -452,11 +650,11 @@ int get_clocks (void) * for that SOC. This information is taken from application note * AN2919. */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ - defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_P1022) gd->arch.i2c1_clk = sys_info.freq_systembus; -#elif defined(CONFIG_MPC8544) +#elif defined(CONFIG_ARCH_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See @@ -475,12 +673,15 @@ int get_clocks (void) gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ - defined(CONFIG_P1014) +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + gd->arch.sdhc_clk = sys_info.freq_sdhc / 2; +#else +#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010) gd->arch.sdhc_clk = gd->bus_clk; #else gd->arch.sdhc_clk = gd->bus_clk / 2; #endif +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2)