X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Finterrupts.c;h=daf46a9ba86d83279a3654e6cef28f0e9f6e98d4;hb=a7a97fddb390b998449264a005ce32a95dfd068b;hp=a62b031774835061aa30054705e027fd6dde5fe0;hpb=2df0e6fc6b71448e1752e4ce1d5577d8977f3e5e;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index a62b031774..daf46a9ba8 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -8,23 +8,7 @@
  * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -32,11 +16,23 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
 
 int interrupt_init_cpu(unsigned int *decrementer_count)
 {
 	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 
+#ifdef CONFIG_POST
+	/*
+	 * The POST word is stored in the PIC's TFRR register which gets
+	 * cleared when the PIC is reset.  Save it off so we can restore it
+	 * later.
+	 */
+	ulong post_word = post_word_load();
+#endif
+
 	out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
 	while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
 		;
@@ -46,7 +42,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count)
 	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 	/* PIE is same as DIE, dec interrupt enable */
-	mtspr(SPRN_TCR, TCR_PIE);
+	mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
 
 #ifdef CONFIG_INTERRUPTS
 	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */
@@ -78,6 +74,10 @@ int interrupt_init_cpu(unsigned int *decrementer_count)
 	pic->ctpr=0;		/* 40080 clear current task priority register */
 #endif
 
+#ifdef CONFIG_POST
+	post_word_store(post_word);
+#endif
+
 	return (0);
 }