X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Ffsl_corenet_serdes.c;h=f5126e2c8acfb5c2b215d8182de1d1070fab09e7;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=4b52dad56cefa08651bb349295569bd9efa96f52;hpb=c1ee16b8e02cd974d7ce9bfb9578e6a1557c2af2;p=oweals%2Fu-boot.git diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 4b52dad56c..f5126e2c8a 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -1,26 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ #include +#include +#include +#include #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 #include #endif @@ -29,7 +15,8 @@ #include #include #include -#include +#include +#include #include "fsl_corenet_serdes.h" /* @@ -46,8 +33,6 @@ static u32 serdes_prtcl_map; -#define HWCONFIG_BUFFER_SIZE 128 - #ifdef DEBUG static const char *serdes_prtcl_str[] = { [NONE] = "NA", @@ -68,6 +53,7 @@ static const char *serdes_prtcl_str[] = { [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", [XAUI_FM1] = "XAUI_FM1", [XAUI_FM2] = "XAUI_FM2", [AURORA] = "DEBUG", @@ -93,10 +79,21 @@ static const struct { { 17, 163, FSL_SRDS_BANK_2 }, { 18, 164, FSL_SRDS_BANK_2 }, { 19, 165, FSL_SRDS_BANK_2 }, +#ifdef CONFIG_ARCH_P4080 { 20, 170, FSL_SRDS_BANK_3 }, { 21, 171, FSL_SRDS_BANK_3 }, { 22, 172, FSL_SRDS_BANK_3 }, { 23, 173, FSL_SRDS_BANK_3 }, +#else + { 20, 166, FSL_SRDS_BANK_3 }, + { 21, 167, FSL_SRDS_BANK_3 }, + { 22, 168, FSL_SRDS_BANK_3 }, + { 23, 169, FSL_SRDS_BANK_3 }, +#endif +#if SRDS_MAX_BANK > 3 + { 24, 175, FSL_SRDS_BANK_4 }, + { 25, 176, FSL_SRDS_BANK_4 }, +#endif }; int serdes_get_lane_idx(int lane) @@ -142,6 +139,9 @@ int is_serdes_configured(enum srds_prtcl device) if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) return 0; + if (!(serdes_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes_prtcl_map; } @@ -483,7 +483,7 @@ static void wait_for_rstdone(unsigned int bank) } -void __soc_serdes_init(void) +static void __soc_serdes_init(void) { /* Allow for SoC-specific initialization in _serdes.c */ }; @@ -494,6 +494,9 @@ void fsl_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; +#ifdef CONFIG_ARCH_P5040 + serdes_corenet_t *srds2_regs; +#endif int lane, bank, idx; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -504,7 +507,7 @@ void fsl_serdes_init(void) size_t arglen; #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 - int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ + int need_serdes_a001; /* true == need work-around for SERDES A001 */ #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; @@ -514,9 +517,11 @@ void fsl_serdes_init(void) * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #endif + if (serdes_prtcl_map & (1 << NONE)) + return; /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -575,8 +580,39 @@ void fsl_serdes_init(void) } } +#ifdef CONFIG_ARCH_P5040 + /* + * Lanes on bank 4 on P5040 are commented-out, but for some SERDES + * protocols, these lanes are routed to SATA. We use serdes_prtcl_map + * to decide whether a protocol is supported on a given lane, so SATA + * will be identified as not supported, and therefore not initialized. + * So for protocols which use SATA on bank4, we add SATA support in + * serdes_prtcl_map. + */ + switch (cfg) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; + break; + default: + srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + + /* We don't need bank 4, so power it down */ + setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); + } +#endif + soc_serdes_init(); + /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1 << NONE); + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 /* * Bank two uses the clock from bank three, so if bank two is enabled, @@ -618,6 +654,38 @@ void fsl_serdes_init(void) } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A004699 + /* + * To avoid the situation that resulted in the P4080 erratum + * SERDES-8, a given SerDes bank will use the PLLs from the previous + * bank if one of the PLL frequencies is a multiple of the other. For + * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, + * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says + * that, in this situation, lane synchronization is not initiated. So + * when we detect a bank with a "borrowed" PLL, we have to manually + * initiate lane synchronization. + */ + for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { + /* Determine the first lane for this bank */ + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) + if (lanes[lane].bank == bank) + break; + idx = lanes[lane].idx; + + /* + * Check if the PLL for the bank is borrowed. The UOTHL + * bit of the first lane will tell us that. + */ + if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { + /* Manually start lane synchronization */ + setbits_be32(&srds_regs->bank[bank].pllcr0, + SRDS_PLLCR0_PVCOCNT_EN); + } + } +#endif + #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl; @@ -645,9 +713,13 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 /* - * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for - * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or - * AURORA before the device is initialized. + * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 + * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, + * or AURORA before the device is initialized. + * + * Note that this part of the SERDES-9 work-around is + * redundant if the work-around for A-4580 has already been + * applied via PBI. */ switch (lane_prtcl) { case SGMII_FM1_DTSEC1: @@ -658,15 +730,18 @@ void fsl_serdes_init(void) case SGMII_FM2_DTSEC2: case SGMII_FM2_DTSEC3: case SGMII_FM2_DTSEC4: + case SGMII_FM2_DTSEC5: case XAUI_FM1: case XAUI_FM2: case SRIO1: case SRIO2: case AURORA: - clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, - SRDS_TTLCR0_FLT_SEL_MASK, - SRDS_TTLCR0_FLT_SEL_750PPM | - SRDS_TTLCR0_PM_DIS); + out_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_KFR_26 | + SRDS_TTLCR0_FLT_SEL_KPH_28 | + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_FREQOVD_EN); + break; default: break; } @@ -717,6 +792,10 @@ void fsl_serdes_init(void) serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | FSL_CORENET_DEVDISR2_DTSEC2_4; break; + case SGMII_FM2_DTSEC5: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_5; + break; case XAUI_FM1: serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | FSL_CORENET_DEVDISR2_10GEC1; @@ -790,3 +869,20 @@ void fsl_serdes_init(void) } #endif } + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} +