X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fcpu_init_early.c;h=40cb24dd54a04ac393284bb03b88edc3b9e565eb;hb=c590e62d3b6f6dd72eae1183614f919e3fd7ffcb;hp=998781b706bc22667313053c3b055e773975f8a3;hpb=e7f9350525d73233d4eaf1793f8fe618e9fd4910;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 998781b706..40cb24dd54 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -15,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
 
@@ -70,9 +69,9 @@ void setup_ifc(void)
 #endif
 
 	/* Change flash's physical address */
-	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
 
 	return ;
 }
@@ -82,7 +81,6 @@ void setup_ifc(void)
 void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
-	int i;
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
@@ -90,23 +88,21 @@ void cpu_init_early_f(void *fdt)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
+	int i;
 #endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
-	/*
-	 * Clear initial global data
-	 *   we don't use memset so we can share this code with NAND_SPL
-	 */
-	for (i = 0; i < sizeof(gd_t); i++)
-		((char *)gd)[i] = 0;
+	/* gd area was zeroed during startup */
 
+#ifdef CONFIG_ARCH_QEMU_E500
 	/*
 	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
 	 * so we need to populate it before it accesses it.
 	 */
 	gd->fdt_blob = fdt;
+#endif
 
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
@@ -159,9 +155,12 @@ void cpu_init_early_f(void *fdt)
 	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
 	dst = (u32 *) SRAM_BASE_ADDR;
 	src = (u32 *) setup_ifc;
-	for (i = 0; i < 1024; i++)
+	for (i = 0; i < 1024; i++) {
+		/* cppcheck-suppress nullPointer */
 		*dst++ = *src++;
+	}
 
+	/* cppcheck-suppress nullPointer */
 	setup_ifc_sram();
 
 	/* CLEANUP */