X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc83xx%2Fcpu.c;h=c3e25978a807b3d4fa54cd2f3be10713dc6a54d7;hb=36bf446b642d5759981f5adf547b4a7aeb15eee3;hp=82370b54301e583ad4de60c5e9c8a5a0a70cadf4;hpb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;p=oweals%2Fu-boot.git

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 82370b5430..c3e25978a8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -10,6 +10,9 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <vsprintf.h>
 #include <watchdog.h>
 #include <command.h>
 #include <mpc83xx.h>
@@ -18,13 +21,14 @@
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
 #include <linux/immap_qe.h>
 #include <asm/io.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_CPU_MPC83XX
 int checkcpu(void)
 {
 	volatile immap_t *immr;
@@ -114,7 +118,9 @@ int checkcpu(void)
 
 	return 0;
 }
+#endif
 
+#ifndef CONFIG_SYSRESET
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
@@ -130,18 +136,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #ifdef MPC83xx_RESET
 
 	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+	msr = mfmsr();
+	msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+	mtmsr(msr);
 
 	/* enable Reset Control Reg */
 	immap->reset.rpr = 0x52535445;
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("isync");
+	sync();
+	isync();
 
 	/* confirm Reset Control Reg is enabled */
-	while(!((immap->reset.rcer) & RCER_CRE));
+	while(!((immap->reset.rcer) & RCER_CRE))
+		;
 
 	udelay(200);
 
@@ -153,10 +159,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 
 	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
+	msr = mfmsr();
 	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+	mtmsr(msr);
 
 	/*
 	 * Trying to execute the next instruction at a non-existing address
@@ -169,17 +174,17 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 	return 1;
 }
-
+#endif
 
 /*
  * Get timebase clock frequency (like cpu_clk in Hz)
  */
-
+#ifndef CONFIG_TIMER
 unsigned long get_tbclk(void)
 {
 	return (gd->bus_clk + 3L) / 4L;
 }
-
+#endif
 
 #if defined(CONFIG_WATCHDOG)
 void watchdog_reset (void)
@@ -192,10 +197,11 @@ void watchdog_reset (void)
 	immr->wdt.swsrr = 0xaa39;
 
 	if (re_enable)
-		enable_interrupts ();
+		enable_interrupts();
 }
 #endif
 
+#ifndef CONFIG_DM_ETH
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
@@ -211,6 +217,7 @@ int cpu_eth_init(bd_t *bis)
 #endif
 	return 0;
 }
+#endif /* !CONFIG_DM_ETH */
 
 /*
  * Initializes on-chip MMC controllers.
@@ -224,3 +231,21 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+	asm("lfd 1, 0(%1)\n\t"
+	    "stfd 1, 0(%0)"
+	    :
+	    : "r" (addr), "r" (value)
+	    : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+	asm("lfd 1, 0(%0)\n\t"
+	    "stfd 1, 0(%1)"
+	    :
+	    : "r" (addr), "r" (ret)
+	    : "memory");
+}