X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fmips%2FKconfig;h=31b622ff5108a7d4547761a45c69a5745cf67205;hb=fc82e7684ba31a1a6ef721e7d750f37117906a70;hp=c97ea4156b49a78f474b1bf62ea1c16f4c5a2a81;hpb=102d86552abc82818c22b39fdef4b3a280a60643;p=oweals%2Fu-boot.git

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c97ea4156b..31b622ff51 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -14,13 +14,13 @@ choice
 
 config TARGET_QEMU_MIPS
 	bool "Support qemu-mips"
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_BIG_ENDIAN
-	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_CPU_MIPS64_R1
 	select SUPPORTS_CPU_MIPS64_R2
-	select ROM_EXCEPTION_VECTORS
+	select SUPPORTS_LITTLE_ENDIAN
 
 config TARGET_MALTA
 	bool "Support malta"
@@ -28,97 +28,104 @@ config TARGET_MALTA
 	select DM_SERIAL
 	select DYNAMIC_IO_PORT_BASE
 	select MIPS_CM
+	select MIPS_L1_CACHE_SHIFT_6
 	select MIPS_L2_CACHE
 	select OF_CONTROL
 	select OF_ISA_BUS
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_BIG_ENDIAN
-	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_CPU_MIPS32_R6
 	select SUPPORTS_CPU_MIPS64_R1
 	select SUPPORTS_CPU_MIPS64_R2
 	select SUPPORTS_CPU_MIPS64_R6
+	select SUPPORTS_LITTLE_ENDIAN
 	select SWAP_IO_SPACE
-	select MIPS_L1_CACHE_SHIFT_6
-	select ROM_EXCEPTION_VECTORS
+	imply CMD_DM
 
 config TARGET_VCT
 	bool "Support vct"
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_BIG_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
-	select ROM_EXCEPTION_VECTORS
 
 config TARGET_DBAU1X00
 	bool "Support dbau1x00"
+	select MIPS_TUNE_4KC
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_BIG_ENDIAN
-	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_LITTLE_ENDIAN
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
-	select ROM_EXCEPTION_VECTORS
-	select MIPS_TUNE_4KC
 
 config TARGET_PB1X00
 	bool "Support pb1x00"
-	select SUPPORTS_LITTLE_ENDIAN
+	select MIPS_TUNE_4KC
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_LITTLE_ENDIAN
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
-	select ROM_EXCEPTION_VECTORS
-	select MIPS_TUNE_4KC
 
 config ARCH_ATH79
 	bool "Support QCA/Atheros ath79"
-	select OF_CONTROL
 	select DM
+	select OF_CONTROL
+	imply CMD_DM
 
 config ARCH_BMIPS
 	bool "Support BMIPS SoCs"
-	select OF_CONTROL
-	select DM
 	select CLK
 	select CPU
+	select DM
+	select OF_CONTROL
 	select RAM
 	select SYSRESET
+	imply CMD_DM
 
 config MACH_PIC32
 	bool "Support Microchip PIC32"
-	select OF_CONTROL
 	select DM
+	select OF_CONTROL
+	imply CMD_DM
 
 config TARGET_BOSTON
 	bool "Support Boston"
 	select DM
 	select DM_SERIAL
-	select OF_CONTROL
 	select MIPS_CM
 	select MIPS_L1_CACHE_SHIFT_6
 	select MIPS_L2_CACHE
+	select OF_BOARD_SETUP
+	select OF_CONTROL
+	select ROM_EXCEPTION_VECTORS
 	select SUPPORTS_BIG_ENDIAN
-	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_CPU_MIPS32_R6
 	select SUPPORTS_CPU_MIPS64_R1
 	select SUPPORTS_CPU_MIPS64_R2
 	select SUPPORTS_CPU_MIPS64_R6
-	select ROM_EXCEPTION_VECTORS
+	select SUPPORTS_LITTLE_ENDIAN
+	imply CMD_DM
 
 config TARGET_XILFPGA
 	bool "Support Imagination Xilfpga"
-	select OF_CONTROL
 	select DM
-	select DM_SERIAL
-	select DM_GPIO
 	select DM_ETH
-	select SUPPORTS_LITTLE_ENDIAN
-	select SUPPORTS_CPU_MIPS32_R1
-	select SUPPORTS_CPU_MIPS32_R2
+	select DM_GPIO
+	select DM_SERIAL
 	select MIPS_L1_CACHE_SHIFT_4
+	select OF_CONTROL
 	select ROM_EXCEPTION_VECTORS
+	select SUPPORTS_CPU_MIPS32_R1
+	select SUPPORTS_CPU_MIPS32_R2
+	select SUPPORTS_LITTLE_ENDIAN
+	imply CMD_DM
 	help
 	  This supports IMGTEC MIPSfpga platform
 
@@ -221,6 +228,17 @@ config ROM_EXCEPTION_VECTORS
 	  Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
 	  In that case the image size will be reduced by 0x500 bytes.
 
+config MIPS_CM_BASE
+	hex "MIPS CM GCR Base Address"
+	depends on MIPS_CM
+	default 0x16100000 if TARGET_BOSTON
+	default 0x1fbf8000
+	help
+	  The physical base address at which to map the MIPS Coherence Manager
+	  Global Configuration Registers (GCRs). This should be set such that
+	  the GCRs occupy a region of the physical address space which is
+	  otherwise unused, or at minimum that software doesn't need to access.
+
 endmenu
 
 menu "OS boot interface"
@@ -393,15 +411,6 @@ config MIPS_CM
 	  wish U-Boot to configure it or make use of it to retrieve system
 	  information such as cache configuration.
 
-config MIPS_CM_BASE
-	hex
-	default 0x1fbf8000
-	help
-	  The physical base address at which to map the MIPS Coherence Manager
-	  Global Configuration Registers (GCRs). This should be set such that
-	  the GCRs occupy a region of the physical address space which is
-	  otherwise unused, or at minimum that software doesn't need to access.
-
 endif
 
 endmenu