X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fmips%2FKconfig;h=31b622ff5108a7d4547761a45c69a5745cf67205;hb=fc82e7684ba31a1a6ef721e7d750f37117906a70;hp=53363e38fe4309fa751716ce1d25a12d6d0e3d58;hpb=6523dbf7cce8d8c903346f756e0e41e46ce6d6b9;p=oweals%2Fu-boot.git diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 53363e38fe..31b622ff51 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,30 +14,39 @@ choice config TARGET_QEMU_MIPS bool "Support qemu-mips" + select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN - select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_LITTLE_ENDIAN config TARGET_MALTA bool "Support malta" select DM select DM_SERIAL select DYNAMIC_IO_PORT_BASE + select MIPS_CM + select MIPS_L1_CACHE_SHIFT_6 + select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS + select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN - select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS32_R6 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_CPU_MIPS64_R6 + select SUPPORTS_LITTLE_ENDIAN select SWAP_IO_SPACE - select MIPS_L1_CACHE_SHIFT_6 + imply CMD_DM config TARGET_VCT bool "Support vct" + select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 @@ -45,39 +54,92 @@ config TARGET_VCT config TARGET_DBAU1X00 bool "Support dbau1x00" + select MIPS_TUNE_4KC + select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN - select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN select SYS_MIPS_CACHE_INIT_RAM_LOAD - select MIPS_TUNE_4KC config TARGET_PB1X00 bool "Support pb1x00" - select SUPPORTS_LITTLE_ENDIAN + select MIPS_TUNE_4KC + select ROM_EXCEPTION_VECTORS select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN select SYS_MIPS_CACHE_INIT_RAM_LOAD - select MIPS_TUNE_4KC config ARCH_ATH79 bool "Support QCA/Atheros ath79" + select DM select OF_CONTROL + imply CMD_DM + +config ARCH_BMIPS + bool "Support BMIPS SoCs" + select CLK + select CPU select DM + select OF_CONTROL + select RAM + select SYSRESET + imply CMD_DM config MACH_PIC32 bool "Support Microchip PIC32" + select DM select OF_CONTROL + imply CMD_DM + +config TARGET_BOSTON + bool "Support Boston" select DM + select DM_SERIAL + select MIPS_CM + select MIPS_L1_CACHE_SHIFT_6 + select MIPS_L2_CACHE + select OF_BOARD_SETUP + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_CPU_MIPS32_R6 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_CPU_MIPS64_R6 + select SUPPORTS_LITTLE_ENDIAN + imply CMD_DM + +config TARGET_XILFPGA + bool "Support Imagination Xilfpga" + select DM + select DM_ETH + select DM_GPIO + select DM_SERIAL + select MIPS_L1_CACHE_SHIFT_4 + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + imply CMD_DM + help + This supports IMGTEC MIPSfpga platform endchoice source "board/dbau1x00/Kconfig" +source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" +source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" if MIPS @@ -154,6 +216,31 @@ config CPU_MIPS64_R6 endchoice +menu "General setup" + +config ROM_EXCEPTION_VECTORS + bool "Build U-Boot image with exception vectors" + help + Enable this to include exception vectors in the U-Boot image. This is + required if the U-Boot entry point is equal to the address of the + CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, + U-Boot booted from parallel NOR flash). + Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). + In that case the image size will be reduced by 0x500 bytes. + +config MIPS_CM_BASE + hex "MIPS CM GCR Base Address" + depends on MIPS_CM + default 0x16100000 if TARGET_BOSTON + default 0x1fbf8000 + help + The physical base address at which to map the MIPS Coherence Manager + Global Configuration Registers (GCRs). This should be set such that + the GCRs occupy a region of the physical address space which is + otherwise unused, or at minimum that software doesn't need to access. + +endmenu + menu "OS boot interface" config MIPS_BOOT_CMDLINE_LEGACY @@ -225,6 +312,9 @@ config MIPS_TUNE_14KC config MIPS_TUNE_24KC bool +config MIPS_TUNE_34KC + bool + config MIPS_TUNE_74KC bool @@ -240,6 +330,51 @@ config SWAP_IO_SPACE config SYS_MIPS_CACHE_INIT_RAM_LOAD bool +config MIPS_INIT_STACK_IN_SRAM + bool + default n + help + Select this if the initial stack frame could be setup in SRAM. + Normally the initial stack frame is set up in DRAM which is often + only available after lowlevel_init. With this option the initial + stack frame and the early C environment is set up before + lowlevel_init. Thus lowlevel_init does not need to be implemented + in assembler. + +config SYS_DCACHE_SIZE + int + default 0 + help + The total size of the L1 Dcache, if known at compile time. + +config SYS_DCACHE_LINE_SIZE + int + default 0 + help + The size of L1 Dcache lines, if known at compile time. + +config SYS_ICACHE_SIZE + int + default 0 + help + The total size of the L1 ICache, if known at compile time. + +config SYS_ICACHE_LINE_SIZE + int + default 0 + help + The size of L1 Icache lines, if known at compile time. + +config SYS_CACHE_SIZE_AUTO + def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ + SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 + help + Select this (or let it be auto-selected by not defining any cache + sizes) in order to allow U-Boot to automatically detect the sizes + of caches at runtime. This has a small cost in code size & runtime + so if you know the cache configuration for your system at compile + time it would be beneficial to configure it. + config MIPS_L1_CACHE_SHIFT_4 bool @@ -260,9 +395,22 @@ config MIPS_L1_CACHE_SHIFT default "4" if MIPS_L1_CACHE_SHIFT_4 default "5" +config MIPS_L2_CACHE + bool + help + Select this if your system includes an L2 cache and you want U-Boot + to initialise & maintain it. + config DYNAMIC_IO_PORT_BASE bool +config MIPS_CM + bool + help + Select this if your system contains a MIPS Coherence Manager and you + wish U-Boot to configure it or make use of it to retrieve system + information such as cache configuration. + endif endmenu