X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fm68k%2Finclude%2Fasm%2Fcache.h;h=f9e2d15f43f0bfa7ba5e2a26fbffb8365a7b4c2d;hb=612404c28a64a6df300642a1550a65dcc8e01f82;hp=7c84e4847119be2665fb8ba418f17f54b8c070b7;hpb=819833af39a91fa1c1e8252862bbda6f5a602f7b;p=oweals%2Fu-boot.git diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 7c84e48471..f9e2d15f43 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -1,7 +1,7 @@ /* * ColdFire cache * - * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * Copyright 2004-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -37,10 +37,9 @@ #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) #define CONFIG_CF_V4 -#if defined(CONFIG_MCF5441x) +#elif defined(CONFIG_MCF5441x) #define CONFIG_CF_V4E /* Four Extra ACRn */ #endif -#endif /* ***** CACR ***** */ /* V2 Core */ @@ -87,7 +86,7 @@ #endif /* CONFIG_CF_V3 */ /* V4 Core */ -#ifdef CONFIG_CF_V4 +#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) #define CF_CACR_DEC (1 << 31) #define CF_CACR_DW (1 << 30) @@ -113,7 +112,7 @@ #define CF_CACR_IDSP (1 << 7) #define CF_CACR_EUSP (1 << 5) -#ifdef CONFIG_MCF5445x +#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) #define CF_CACR_IVO (1 << 20) #define CF_CACR_SPA (1 << 14) #else @@ -148,7 +147,7 @@ #endif /* CONFIG_CF_V2 */ /* V4 Core */ -#ifdef CONFIG_CF_V4 +#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) #define CF_ACR_AMM (1 << 10) #define CF_ACR_SP (1 << 3) #endif /* CONFIG_CF_V4 */ @@ -207,4 +206,14 @@ void dcache_invalid(void); #endif +/* + * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer + * alignment unless the board configuration has specified a new value. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + #endif /* __CACHE_H */