X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fm68k%2Fcpu%2Fmcf5227x%2Fcpu_init.c;h=3bbc42f508ceda6cdf0d62174ce08d0f214c9ea9;hb=cad28d37d5146cf293fe841c7c8e6f658c8a4940;hp=91b5fadc8809493d3a97b232d8cea9247fdf7139;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=oweals%2Fu-boot.git

diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index 91b5fadc88..3bbc42f508 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *
  * (C) Copyright 2000-2003
@@ -5,8 +6,6 @@
  *
  * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -17,6 +16,15 @@
 #include <asm/rtc.h>
 #include <linux/compiler.h>
 
+void cfspi_port_conf(void)
+{
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	out_8(&gpio->par_dspi,
+	      GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	      GPIO_PAR_DSPI_SCK_SCK);
+}
+
 /*
  * Breath some life into the CPU...
  *
@@ -94,6 +102,8 @@ void cpu_init_f(void)
 #endif
 
 	icache_enable();
+
+	cfspi_port_conf();
 }
 
 /*
@@ -138,57 +148,3 @@ void uart_port_conf(int port)
 		break;
 	}
 }
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	out_8(&gpio->par_dspi,
-		GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-		GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
-		return -1;
-
-	/* Clear FIFO and resume transfer */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
-		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
-		break;
-	}
-
-	return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
-	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Clear FIFO */
-	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
-		break;
-	}
-}
-#endif