X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fblackfin%2Finclude%2Fasm%2Fcplb.h;h=420380dab1cb8c2628ba15f7a3e95cec9a60b2ae;hb=6853e6aa77b388998a5368b400aee3ae7776b1c2;hp=cc21e93a18546e9793caf7a621e9a5df527c7b0d;hpb=819833af39a91fa1c1e8252862bbda6f5a602f7b;p=oweals%2Fu-boot.git

diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index cc21e93a18..420380dab1 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -46,8 +46,13 @@
 #define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
 
 /* Data Attibutes*/
-
-#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#if defined(__ADSPBF60x__)
+#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
+				CPLB_USER_RD | CPLB_VALID)
+#else
+#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
+				CPLB_USER_RD | CPLB_VALID)
+#endif
 #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
@@ -59,14 +64,32 @@
 #endif
 
 #ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
+				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
+				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
+				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
+				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 
 #else				/*Write Through */
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
+				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
+				CPLB_USER_WR | CPLB_VALID | \
+				ANOMALY_05000158_WORKAROUND)
+#else
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
+				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
+				CPLB_USER_WR | CPLB_VALID | \
+				ANOMALY_05000158_WORKAROUND)
+#endif
 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
 #define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)