X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Fblackfin%2Fcpu%2Fcpu.c;h=6a0bcca9f921187acdfa5e15deca275881110ad4;hb=c68436fa427a69ea308d74c410067507d6c7103b;hp=2c8fd86b86f939e19cf897d1f43237a3ab57b4ad;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=oweals%2Fu-boot.git

diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index 2c8fd86b86..6a0bcca9f9 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -19,6 +19,7 @@
 
 #include "cpu.h"
 #include "serial.h"
+#include "initcode.h"
 
 ulong bfin_poweron_retx;
 
@@ -44,13 +45,16 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 		extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
 		memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
 	}
-#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-	/* The BF537 bootrom will reset the EBIU_AMGCTL register on us
-	 * after it has finished loading the LDR.  So configure it again.
+
+	/*
+	 * Make sure our async settings are committed.  Some bootroms
+	 * (like the BF537) will reset some registers on us after it
+	 * has finished loading the LDR.  Or if we're booting over
+	 * JTAG, the initcode never got a chance to run.  Or if we
+	 * aren't booting from parallel flash, the initcode skipped
+	 * this step completely.
 	 */
-	else
-		bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
+	program_async_controller(NULL);
 
 	/* Save RETX so we can pass it while booting Linux */
 	bfin_poweron_retx = bootflag;
@@ -91,7 +95,9 @@ int irq_init(void)
 #else
 	bfin_write_SIC_IMASK(0);
 #endif
-	bfin_write_EVT2(evt_default);	/* NMI */
+	/* Set up a dummy NMI handler if needed.  */
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
+		bfin_write_EVT2(evt_nmi);	/* NMI */
 	bfin_write_EVT5(evt_default);	/* hardware error */
 	bfin_write_EVT6(evt_default);	/* core timer */
 	bfin_write_EVT7(evt_default);