X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fsc64-regs.h;h=d3aa18530d97593bd0b43ce071f10363d59f09d6;hb=ebc4ef61d76fc182773fe225151adc9b913c62eb;hp=1e52bb1ef165654debc203668ac26f3fe30389fa;hpb=682e09ff9f3514e79ee3382988b74f63b4bdd06b;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index 1e52bb1ef1..d3aa18530d 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -13,12 +13,14 @@
 #define SC_BASE_ADDR		0x61840000
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD20: CPU/ARM */
-#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD20: misc */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD11/20: CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD11/20: misc */
 #define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* LD20: IPP */
-#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD20: Video codec */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD11/20: Video codec */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD11 */
 #define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD20: VPE etc. */
 #define SC_GPPLLCTRL	(SC_BASE_ADDR | 0x1450)	/* LD20: GPU/Mali */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* LD11: DDR memory */
 #define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1460)	/* LD20: DDR memory 0 */
 #define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1470)	/* LD20: DDR memory 1 */
 #define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x1480)	/* LD20: DDR memory 2 */
@@ -50,6 +52,8 @@
 #define SC_CLKCTRL		(SC_BASE_ADDR | 0x2100)
 #define SC_CLKCTRL3		(SC_BASE_ADDR | 0x2108)
 #define SC_CLKCTRL4		(SC_BASE_ADDR | 0x210c)
+#define   SC_CLKCTRL4_MIO		(1 << 10)
+#define   SC_CLKCTRL4_STDMAC		(1 << 8)
 #define   SC_CLKCTRL4_PERI		(1 << 7)
 #define   SC_CLKCTRL4_ETHER		(1 << 6)
 #define   SC_CLKCTRL4_NAND		(1 << 0)
@@ -61,4 +65,12 @@
 #define   SC_CLKCTRL7_UMC31		(1 << 1)
 #define   SC_CLKCTRL7_UMC30		(1 << 0)
 
+#define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8000)
+#define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8004)
+#define SC_CA72_GEARUPD		(SC_BASE_ADDR | 0x8008)
+#define SC_CA53_GEARST		(SC_BASE_ADDR | 0x8080)
+#define SC_CA53_GEARSET		(SC_BASE_ADDR | 0x8084)
+#define SC_CA53_GEARUPD		(SC_BASE_ADDR | 0x8088)
+#define   SC_CA_GEARUPD			(1 << 0)
+
 #endif /* SC64_REGS_H */