X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fdram_init.c;h=7f2753190c233372e21c9f9da81ee9fc1b6a6453;hb=60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22;hp=d9f6c16fdc2554375f82d28eb8c322ef1e32a0e6;hpb=d38de7cb03adf88e18c05d840c2528b7a5af2f9b;p=oweals%2Fu-boot.git diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index d9f6c16fdc..7f2753190c 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -1,104 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2012-2015 Panasonic Corporation * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ */ -#include -#include +#include #include +#include +#include +#include #include +#include +#include +#include "init.h" #include "sg-regs.h" #include "soc-info.h" -#define pr_warn(fmt, args...) printf(fmt, ##args) -#define pr_err(fmt, args...) printf(fmt, ##args) - DECLARE_GLOBAL_DATA_PTR; -struct uniphier_memif_data { - unsigned int soc_id; - unsigned long sparse_ch1_base; - int have_ch2; -}; - -static const struct uniphier_memif_data uniphier_memif_data[] = { - { - .soc_id = UNIPHIER_SLD3_ID, - .sparse_ch1_base = 0xc0000000, - /* - * In fact, SLD3 has DRAM ch2, but the memory regions for ch1 - * and ch2 overlap, and host cannot get access to them at the - * same time. Hide the ch2 from U-Boot. - */ - }, - { - .soc_id = UNIPHIER_LD4_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO4_ID, - .sparse_ch1_base = 0xa0000000, - }, - { - .soc_id = UNIPHIER_SLD8_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PRO5_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_PXS2_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD6B_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_LD11_ID, - .sparse_ch1_base = 0xc0000000, - }, - { - .soc_id = UNIPHIER_LD20_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, - { - .soc_id = UNIPHIER_PXS3_ID, - .sparse_ch1_base = 0xc0000000, - .have_ch2 = 1, - }, -}; -UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) - struct uniphier_dram_map { unsigned long base; unsigned long size; }; -static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) +static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map, + unsigned long sparse_ch1_base, bool have_ch2) { - const struct uniphier_memif_data *data; unsigned long size; u32 val; - data = uniphier_get_memif_data(); - if (!data) { - pr_err("unsupported SoC\n"); - return -EINVAL; - } - - val = readl(SG_MEMCONF); + val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ - dram_map[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = 0x80000000; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -130,14 +66,14 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].base = dram_map[0].base + size; if (val & SG_MEMCONF_SPARSEMEM) { - if (dram_map[1].base > data->sparse_ch1_base) { + if (dram_map[1].base > sparse_ch1_base) { pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); pr_warn("Only ch0 is available\n"); dram_map[1].base = 0; return 0; } - dram_map[1].base = data->sparse_ch1_base; + dram_map[1].base = sparse_ch1_base; } switch (val & SG_MEMCONF_CH1_SZ_MASK) { @@ -166,7 +102,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) dram_map[1].size = size; - if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE) + if (!have_ch2 || val & SG_MEMCONF_CH2_DISABLE) return 0; /* set up ch2 */ @@ -201,82 +137,168 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) return 0; } +static int uniphier_ld4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, false); +} + +static int uniphier_pro4_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xa0000000, false); +} + +static int uniphier_pxs2_dram_map_get(struct uniphier_dram_map dram_map[]) +{ + return uniphier_memconf_decode(dram_map, 0xc0000000, true); +} + +struct uniphier_dram_init_data { + unsigned int soc_id; + int (*dram_map_get)(struct uniphier_dram_map dram_map[]); +}; + +static const struct uniphier_dram_init_data uniphier_dram_init_data[] = { + { + .soc_id = UNIPHIER_LD4_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO4_ID, + .dram_map_get = uniphier_pro4_dram_map_get, + }, + { + .soc_id = UNIPHIER_SLD8_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PRO5_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS2_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD6B_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD11_ID, + .dram_map_get = uniphier_ld4_dram_map_get, + }, + { + .soc_id = UNIPHIER_LD20_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, + { + .soc_id = UNIPHIER_PXS3_ID, + .dram_map_get = uniphier_pxs2_dram_map_get, + }, +}; +UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_dram_init_data, + uniphier_dram_init_data) + +static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map) +{ + const struct uniphier_dram_init_data *data; + + data = uniphier_get_dram_init_data(); + if (!data) { + pr_err("unsupported SoC\n"); + return -ENOTSUPP; + } + + return data->dram_map_get(dram_map); +} + int dram_init(void) { struct uniphier_dram_map dram_map[3] = {}; + bool valid_bank_found = false; + unsigned long prev_top; int ret, i; gd->ram_size = 0; - ret = uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); if (ret) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { + unsigned long max_size; if (!dram_map[i].size) - break; + continue; /* * U-Boot relocates itself to the tail of the memory region, * but it does not expect sparse memory. We use the first * contiguous chunk here. */ - if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < - dram_map[i].base) + if (valid_bank_found && prev_top < dram_map[i].base) + break; + + /* + * Do not use memory that exceeds 32bit address range. U-Boot + * relocates itself to the end of the effectively available RAM. + * This could be a problem for DMA engines that do not support + * 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.) + */ + if (dram_map[i].base >= 1ULL << 32) break; - gd->ram_size += dram_map[i].size; + max_size = (1ULL << 32) - dram_map[i].base; + + gd->ram_size = min(dram_map[i].size, max_size); + + if (!valid_bank_found) + gd->ram_base = dram_map[i].base; + + prev_top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; } + /* + * LD20 uses the last 64 byte for each channel for dynamic + * DDR PHY training + */ + if (uniphier_get_soc_id() == UNIPHIER_LD20_ID) + gd->ram_size -= 64; + return 0; } -void dram_init_banksize(void) +int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; - int i; + unsigned long base, top; + bool valid_bank_found = false; + int ret, i; - uniphier_memconf_decode(dram_map); + ret = uniphier_dram_map_get(dram_map); + if (ret) + return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i >= ARRAY_SIZE(gd->bd->bi_dram)) - break; - - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; - } -} - -#ifdef CONFIG_OF_BOARD_SETUP -/* - * The DRAM PHY requires 64 byte scratch area in each DRAM channel - * for its dynamic PHY training feature. - */ -int ft_board_setup(void *fdt, bd_t *bd) -{ - unsigned long rsv_addr; - const unsigned long rsv_size = 64; - int i, ret; - - if (uniphier_get_soc_id() != UNIPHIER_LD20_ID) - return 0; + if (i < ARRAY_SIZE(gd->bd->bi_dram)) { + gd->bd->bi_dram[i].start = dram_map[i].base; + gd->bd->bi_dram[i].size = dram_map[i].size; + } - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { - if (!gd->bd->bi_dram[i].size) + if (!dram_map[i].size) continue; - rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size; - rsv_addr -= rsv_size; + if (!valid_bank_found) + base = dram_map[i].base; + top = dram_map[i].base + dram_map[i].size; + valid_bank_found = true; + } - ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); - if (ret) - return -ENOSPC; + if (!valid_bank_found) + return -EINVAL; - printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", - rsv_addr, rsv_size); - } + /* map all the DRAM regions */ + uniphier_mem_map_init(base, top - base); return 0; } -#endif