X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fdram%2Fcmd_ddrphy.c;h=ca519d1c7e0c6be37d0ef00cbbc30b72a763fcc4;hb=6717e154473bc44110ae0c6264c2ab84a43579de;hp=3dae12963b9faaaecbba7249a1a7c141a2210cd2;hpb=6dd34ae4c4cce6a4b9f62c9be55b343a6f0a35f8;p=oweals%2Fu-boot.git diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index 3dae12963b..ca519d1c7e 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -1,17 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. + * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include +#include #include +#include #include #include "../soc-info.h" -#include "ddrphy-init.h" #include "ddrphy-regs.h" /* Select either decimal or hexadecimal */ @@ -23,23 +23,55 @@ /* field separator */ #define FS " " -static unsigned long uniphier_ld4_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ -}; +#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p)) + +#define UNIPHIER_MAX_NR_DDRPHY 4 -static unsigned long uniphier_pro4_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ +struct uniphier_ddrphy_param { + unsigned int soc_id; + unsigned int nr_phy; + struct { + resource_size_t base; + unsigned int nr_dx; + } phy[UNIPHIER_MAX_NR_DDRPHY]; }; -static unsigned long uniphier_sld8_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ +static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = { + { + .soc_id = UNIPHIER_LD4_ID, + .nr_phy = 2, + .phy = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + }, + }, + { + .soc_id = UNIPHIER_PRO4_ID, + .nr_phy = 4, + .phy = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5bc02000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + { .base = 0x5be02000, .nr_dx = 2, }, + }, + }, + { + .soc_id = UNIPHIER_SLD8_ID, + .nr_phy = 2, + .phy = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + }, + }, + { + .soc_id = UNIPHIER_LD11_ID, + .nr_phy = 1, + .phy = { + { .base = 0x5bc01000, .nr_dx = 4, }, + }, + }, }; +UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param) static void print_bdl(void __iomem *reg, int n) { @@ -50,18 +82,18 @@ static void print_bdl(void __iomem *reg, int n) printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f); } -static void dump_loop(unsigned long *base, +static void dump_loop(const struct uniphier_ddrphy_param *param, void (*callback)(void __iomem *)) { void __iomem *phy_base, *dx_base; - int p, dx; + int phy, dx; - for (p = 0; *base; base++, p++) { - phy_base = ioremap(*base, SZ_4K); + for (phy = 0; phy < param->nr_phy; phy++) { + phy_base = ioremap(param->phy[phy].base, SZ_4K); dx_base = phy_base + PHY_DX_BASE; - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { - printf("PHY%dDX%d:", p, dx); + for (dx = 0; dx < param->phy[phy].nr_dx; dx++) { + printf("PHY%dDX%d:", phy, dx); (*callback)(dx_base); dx_base += PHY_DX_STRIDE; printf("\n"); @@ -80,12 +112,12 @@ static void __wbdl_dump(void __iomem *dx_base) readl(dx_base + PHY_DX_LCDLR1) & 0xff); } -static void wbdl_dump(unsigned long *base) +static void wbdl_dump(const struct uniphier_ddrphy_param *param) { printf("\n--- Write Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); - dump_loop(base, &__wbdl_dump); + dump_loop(param, &__wbdl_dump); } static void __rbdl_dump(void __iomem *dx_base) @@ -97,12 +129,12 @@ static void __rbdl_dump(void __iomem *dx_base) (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff); } -static void rbdl_dump(unsigned long *base) +static void rbdl_dump(const struct uniphier_ddrphy_param *param) { printf("\n--- Read Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); - dump_loop(base, &__rbdl_dump); + dump_loop(param, &__rbdl_dump); } static void __wld_dump(void __iomem *dx_base) @@ -120,12 +152,12 @@ static void __wld_dump(void __iomem *dx_base) } } -static void wld_dump(unsigned long *base) +static void wld_dump(const struct uniphier_ddrphy_param *param) { printf("\n--- Write Leveling Delay ---\n"); - printf(" Rank0 Rank1 Rank2 Rank3\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); - dump_loop(base, &__wld_dump); + dump_loop(param, &__wld_dump); } static void __dqsgd_dump(void __iomem *dx_base) @@ -142,53 +174,57 @@ static void __dqsgd_dump(void __iomem *dx_base) } } -static void dqsgd_dump(unsigned long *base) +static void dqsgd_dump(const struct uniphier_ddrphy_param *param) { printf("\n--- DQS Gating Delay ---\n"); - printf(" Rank0 Rank1 Rank2 Rank3\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); - dump_loop(base, &__dqsgd_dump); + dump_loop(param, &__dqsgd_dump); } static void __mdl_dump(void __iomem *dx_base) { int i; u32 mdl = readl(dx_base + PHY_DX_MDLR); + for (i = 0; i < 3; i++) printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); } -static void mdl_dump(unsigned long *base) +static void mdl_dump(const struct uniphier_ddrphy_param *param) { printf("\n--- Master Delay Line ---\n"); printf(" IPRD TPRD MDLD\n"); - dump_loop(base, &__mdl_dump); + dump_loop(param, &__mdl_dump); } #define REG_DUMP(x) \ { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \ - printf("%3d: %-10s: %p : %08x\n", \ - ofst >> PHY_REG_SHIFT, #x, reg, readl(reg)); } + printf("%3d: %-10s: %08x : %08x\n", \ + ofst >> PHY_REG_SHIFT, #x, \ + ptr_to_uint(reg), readl(reg)); } #define DX_REG_DUMP(dx, x) \ { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \ PHY_DX_## x; \ void __iomem *reg = phy_base + ofst; \ - printf("%3d: DX%d%-7s: %p : %08x\n", \ - ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); } + printf("%3d: DX%d%-7s: %08x : %08x\n", \ + ofst >> PHY_REG_SHIFT, (dx), #x, \ + ptr_to_uint(reg), readl(reg)); } -static void reg_dump(unsigned long *base) +static void reg_dump(const struct uniphier_ddrphy_param *param) { void __iomem *phy_base; - int p, dx; + int phy, dx; printf("\n--- DDR PHY registers ---\n"); - for (p = 0; *base; base++, p++) { - phy_base = ioremap(*base, SZ_4K); + for (phy = 0; phy < param->nr_phy; phy++) { + phy_base = ioremap(param->phy[phy].base, SZ_4K); - printf("== PHY%d (base: %p) ==\n", p, phy_base); + printf("== PHY%d (base: %08x) ==\n", + phy, ptr_to_uint(phy_base)); printf(" No: Name : Address : Data\n"); REG_DUMP(RIDR); @@ -216,7 +252,7 @@ static void reg_dump(unsigned long *base) REG_DUMP(MR2); REG_DUMP(MR3); - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + for (dx = 0; dx < param->phy[phy].nr_dx; dx++) { DX_REG_DUMP(dx, GCR); DX_REG_DUMP(dx, GTR); } @@ -225,46 +261,40 @@ static void reg_dump(unsigned long *base) } } -static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { - char *cmd = argv[1]; - unsigned long *base; - - switch (uniphier_get_soc_type()) { - case SOC_UNIPHIER_LD4: - base = uniphier_ld4_base; - break; - case SOC_UNIPHIER_PRO4: - base = uniphier_pro4_base; - break; - case SOC_UNIPHIER_SLD8: - base = uniphier_sld8_base; - break; - default: - printf("unsupported SoC\n"); + const struct uniphier_ddrphy_param *param; + char *cmd; + + param = uniphier_get_ddrphy_param(); + if (!param) { + pr_err("unsupported SoC\n"); return CMD_RET_FAILURE; } if (argc == 1) cmd = "all"; + else + cmd = argv[1]; if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) - wbdl_dump(base); + wbdl_dump(param); if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) - rbdl_dump(base); + rbdl_dump(param); if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) - wld_dump(base); + wld_dump(param); if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) - dqsgd_dump(base); + dqsgd_dump(param); if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) - mdl_dump(base); + mdl_dump(param); if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) - reg_dump(base); + reg_dump(param); return CMD_RET_SUCCESS; }