X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fclk%2Fpll-ld4.c;h=c66031bdd05a13b70fa9901b3d64d34edabef02a;hb=1cdb6148450e851abe1df5d7eb20aa07a409941c;hp=6a145a3baa12752daf1c9abe63e3692d308d2406;hpb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 6a145a3baa..c66031bdd0 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -16,14 +16,14 @@ static void upll_init(void)
 {
 	u32 tmp, clk_mode_upll, clk_mode_axosel;
 
-	tmp = readl(SG_PINMON0);
+	tmp = readl(sg_base + SG_PINMON0);
 	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
 	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
 	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-	tmp = readl(SC_UPLLCTRL);
+	tmp = readl(sc_base + SC_UPLLCTRL);
 	tmp &= ~0x18000000;
-	writel(tmp, SC_UPLLCTRL);
+	writel(tmp, sc_base + SC_UPLLCTRL);
 
 	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
 		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
@@ -38,110 +38,110 @@ static void upll_init(void)
 		}
 	}
 
-	writel(tmp, SC_UPLLCTRL);
+	writel(tmp, sc_base + SC_UPLLCTRL);
 
 	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
 	tmp |= 0x08000000;
-	writel(tmp, SC_UPLLCTRL);
+	writel(tmp, sc_base + SC_UPLLCTRL);
 
 	/* wait 10 usec */
 	udelay(10);
 
 	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
 	tmp |= 0x10000000;
-	writel(tmp, SC_UPLLCTRL);
+	writel(tmp, sc_base + SC_UPLLCTRL);
 }
 
 static void vpll_init(void)
 {
 	u32 tmp, clk_mode_axosel;
 
-	tmp = readl(SG_PINMON0);
+	tmp = readl(sg_base + SG_PINMON0);
 	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
 	/* set 1 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
 	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
 	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
 
 	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
 	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
 	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
 	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
 	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
 	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
 	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
 	tmp &= ~0x0000007f;
 	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
 	tmp &= ~0x0000007f;
 	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
 	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
 	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
 		/* AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
 		tmp &= ~0x000fffff;
 		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
 		tmp &= ~0x000fffff;
 		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27BCTRL3);
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
 	} else {
 		/* AXO: default 24.576MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27ACTRL3);
 		tmp &= ~0x000fffff;
 		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
+		writel(tmp, sc_base + SC_VPLL27ACTRL3);
+		tmp = readl(sc_base + SC_VPLL27BCTRL3);
 		tmp &= ~0x000fffff;
 		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
+		writel(tmp, sc_base + SC_VPLL27BCTRL3);
 	}
 
 	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27ACTRL3);
 	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
+	writel(tmp, sc_base + SC_VPLL27ACTRL3);
+	tmp = readl(sc_base + SC_VPLL27BCTRL3);
 	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
+	writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
 	/* wait 10 usec */
 	udelay(10);
 
 	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27ACTRL2);
 	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27ACTRL2);
+	tmp = readl(sc_base + SC_VPLL27BCTRL2);
 	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
+	writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
 	/* set 0 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27ACTRL);
 	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
+	writel(tmp, sc_base + SC_VPLL27ACTRL);
+	tmp = readl(sc_base + SC_VPLL27BCTRL);
 	tmp |= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
+	writel(tmp, sc_base + SC_VPLL27BCTRL);
 }
 
 void uniphier_ld4_pll_init(void)