X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-tegra%2Fclock.c;h=3bb72331a4290b68916a3990aa73868a93b4ae87;hb=a186d2630bd92d952c953f24c412b492265289ff;hp=3b2b4ffd2a72b4804742cdd961c8d73b91cc53c4;hpb=ae27120c31d58b8bb694d9155bcffdcfae8552a6;p=oweals%2Fu-boot.git diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 3b2b4ffd2a..3bb72331a4 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,17 +1,7 @@ /* * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0 */ /* Tegra SoC common clock control functions */ @@ -126,19 +116,34 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, { struct clk_pll *pll = NULL; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; + struct clk_pll_simple *simple_pll = NULL; u32 misc_data, data; - if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) { pll = get_pll(clkid); + } else { + simple_pll = clock_get_simple_pll(clkid); + if (!simple_pll) { + debug("%s: Uknown simple PLL %d\n", __func__, clkid); + return 0; + } + } /* * pllinfo has the m/n/p and kcp/kvco mask and shift * values for all of the PLLs used in U-Boot, with any * SoC differences accounted for. + * + * Preserve EN_LOCKDET, etc. */ - misc_data = readl(&pll->pll_misc); /* preserve EN_LOCKDET, etc. */ - misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift) | (cpcon << pllinfo->kcp_shift); - misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift) | (lfcon << pllinfo->kvco_shift); + if (pll) + misc_data = readl(&pll->pll_misc); + else + misc_data = readl(&simple_pll->pll_misc); + misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); + misc_data |= cpcon << pllinfo->kcp_shift; + misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); + misc_data |= lfcon << pllinfo->kvco_shift; data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); data |= divp << pllinfo->p_shift; @@ -148,14 +153,8 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, writel(misc_data, &pll->pll_misc); writel(data, &pll->pll_base); } else { - struct clk_pll_simple *pll = clock_get_simple_pll(clkid); - - if (!pll) { - debug("%s: Uknown simple PLL %d\n", __func__, clkid); - return 0; - } - writel(misc_data, &pll->pll_misc); - writel(data, &pll->pll_base); + writel(misc_data, &simple_pll->pll_misc); + writel(data, &simple_pll->pll_base); } /* calculate the stable time */ @@ -207,6 +206,29 @@ int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, return 0; } +static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits) +{ + u32 *reg = get_periph_source_reg(periph_id); + u32 val = readl(reg); + + switch (mux_bits) { + case MASK_BITS_31_30: + val >>= OUT_CLK_SOURCE_31_30_SHIFT; + val &= OUT_CLK_SOURCE_31_30_MASK; + return val; + case MASK_BITS_31_29: + val >>= OUT_CLK_SOURCE_31_29_SHIFT; + val &= OUT_CLK_SOURCE_31_29_MASK; + return val; + case MASK_BITS_31_28: + val >>= OUT_CLK_SOURCE_31_28_SHIFT; + val &= OUT_CLK_SOURCE_31_28_MASK; + return val; + default: + return -1; + } +} + void clock_ll_set_source(enum periph_id periph_id, unsigned source) { clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); @@ -289,9 +311,43 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, enum clock_id parent) { u32 *reg = get_periph_source_reg(periph_id); + unsigned parent_rate = pll_rate[parent]; + int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT; + + switch (periph_id) { + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + case PERIPH_ID_UART5: +#ifdef CONFIG_TEGRA20 + /* There's no divider for these clocks in this SoC. */ + return parent_rate; +#else + /* + * This undoes the +2 in get_rate_from_divider() which I + * believe is incorrect. Ideally we would fix + * get_rate_from_divider(), but... Removing the +2 from + * get_rate_from_divider() would probably require remove the -2 + * from the tail of clk_get_divider() since I believe that's + * only there to invert get_rate_from_divider()'s +2. Observe + * how find_best_divider() uses those two functions together. + * However, doing so breaks other stuff, such as Seaboard's + * display, likely due to clock_set_pllout()'s call to + * clk_get_divider(). Attempting to fix that by making + * clock_set_pllout() subtract 2 from clk_get_divider()'s + * return value doesn't help. In summary this clock driver is + * quite broken but I'm afraid I have no idea how to fix it + * without completely replacing it. + */ + div -= 2; + break; +#endif + default: + break; + } - return get_rate_from_divider(pll_rate[parent], - (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT); + return get_rate_from_divider(parent_rate, div); } /** @@ -364,6 +420,20 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, return 0; } +enum clock_id clock_get_periph_parent(enum periph_id periph_id) +{ + int err, mux_bits, divider_bits, type; + int source; + + err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type); + if (err) + return CLOCK_ID_NONE; + + source = clock_ll_get_source_bits(periph_id, mux_bits); + + return get_periph_clock_id(periph_id, source); +} + unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div) { @@ -452,6 +522,11 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) writel(mask, &clkrst->crc_cpu_cmplx_clr); } +unsigned int __weak clk_m_get_rate(unsigned int parent_rate) +{ + return parent_rate; +} + unsigned clock_get_rate(enum clock_id clkid) { struct clk_pll *pll; @@ -463,6 +538,9 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_OSC) return parent_rate; + if (clkid == CLOCK_ID_CLK_M) + return clk_m_get_rate(parent_rate); + pll = get_pll(clkid); if (!pll) return 0; @@ -474,7 +552,16 @@ unsigned clock_get_rate(enum clock_id clkid) * PLLU uses p_mask/p_shift for VCO on all but T210, * T210 uses normal DIVP. Handled in pllinfo table. */ - divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; +#ifdef CONFIG_TEGRA210 + /* + * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is + * not applied. pllP_out2 does have divp applied. All other pllP_outN + * are divided down from pllP_out0. We only support pllP_out0 in + * U-Boot at the time of writing this comment. + */ + if (clkid != CLOCK_ID_PERIPH) +#endif + divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; do_div(rate, divm); return rate; } @@ -494,7 +581,7 @@ unsigned clock_get_rate(enum clock_id clkid) * @param p post divider(DIVP) * @param cpcon base PLL charge pump(CPCON) * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot - * be overriden), 1 if PLL is already correct + * be overridden), 1 if PLL is already correct */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { @@ -564,7 +651,7 @@ void clock_ll_start_uart(enum periph_id periph_id) reset_set_enable(periph_id, 0); } -#ifdef CONFIG_OF_CONTROL +#if CONFIG_IS_ENABLED(OF_CONTROL) int clock_decode_periph_id(const void *blob, int node) { enum periph_id id; @@ -579,7 +666,7 @@ int clock_decode_periph_id(const void *blob, int node) assert(clock_periph_id_isvalid(id)); return id; } -#endif /* CONFIG_OF_CONTROL */ +#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ int clock_verify(void) { @@ -596,6 +683,8 @@ int clock_verify(void) void clock_init(void) { + int i; + pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); @@ -604,14 +693,29 @@ void clock_init(void) pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); + pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); + debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) { + enum periph_id periph_id; + enum clock_id parent; + int source, mux_bits, divider_bits; + + periph_id = periph_clk_init_table[i].periph_id; + parent = periph_clk_init_table[i].parent_clock_id; + + source = get_periph_clock_source(periph_id, parent, &mux_bits, + ÷r_bits); + clock_ll_set_source_bits(periph_id, mux_bits, source); + } } static void set_avp_clock_source(u32 src)