X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-sunxi%2Fclock_sun6i.c;h=6ca38f73d93cdd897f90c40ad5fc741a47e659d5;hb=1e85aaf3723f0ecd06fcf62e2d2482749e1995d6;hp=ec5b026ef56a18d803fd8a62219da22721a5d83d;hpb=2f92629112a1055ed37f8b05dfcf00c3f1875503;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index ec5b026ef5..6ca38f73d9 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * sun6i specific clock code
  *
@@ -6,8 +7,6 @@
  * Tom Cubie <tangliang@allwinnertech.com>
  *
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -66,11 +65,17 @@ void clock_init_sec(void)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_prcm_reg * const prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
 	setbits_le32(&ccm->ccu_sec_switch,
 		     CCM_SEC_SWITCH_MBUS_NONSEC |
 		     CCM_SEC_SWITCH_BUS_NONSEC |
 		     CCM_SEC_SWITCH_PLL_NONSEC);
+	setbits_le32(&prcm->prcm_sec_switch,
+		     PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
+		     PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
+		     PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
 #endif
 }
 
@@ -113,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
 	if (clk > 1152000000) {
 		k = 2;
 	} else if (clk > 768000000) {
-		k = 3;
+		k = 4;
 		m = 2;
 	}
 
@@ -144,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_SUNXI_DE2
+	const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
+#else
 	const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+#endif
 
 	if (clk == 0) {
 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);