X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2FKconfig;h=dea4ce569f711844a3b41e53d37a432ee053efd0;hb=1b1f2319ca2736dab14e1bd1d49558581763138a;hp=a413ea4d1b4a015293a3a9cd9b70583ecda1c707;hpb=13a3972585af60ec367d209cedbd3601e0c77467;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4d1b..dea4ce569f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -2,9 +2,14 @@ if ARCH_SOCFPGA
 
 config TARGET_SOCFPGA_ARRIA5
 	bool
+	select TARGET_SOCFPGA_GEN5
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool
+	select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+	bool
 
 choice
 	prompt "Altera SOCFPGA board select"
@@ -22,6 +27,14 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+	bool "EBV SoCrates (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -38,11 +51,14 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
@@ -55,5 +71,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif