X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-keystone%2Finclude%2Fmach%2Fhardware.h;h=8ca19bbcdbe914f31a913b48ea0102474e460ccd;hb=88033d737d9f46e7eebda6a8f9770957eb9aae9c;hp=f98a24eb5738cdd7cd76e27239ccadfbe370e0ec;hpb=13a3972585af60ec367d209cedbd3601e0c77467;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index f98a24eb57..8ca19bbcdb 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -52,6 +52,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
 
+#define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
+#define KS2_DDRPHY_DATX8_5_OFFSET       0x300
+#define KS2_DDRPHY_DATX8_6_OFFSET       0x340
+#define KS2_DDRPHY_DATX8_7_OFFSET       0x380
 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
 
 #define IODDRM_MASK                     0x00000180
@@ -121,8 +125,13 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
 
 /* NETCP pktdma */
+#ifdef CONFIG_SOC_K2G
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	113
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	114
+#else
 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+#endif
 
 /* Chip Interrupt Controller */
 #define KS2_CIC2_BASE			0x02608000
@@ -143,12 +152,15 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
 #define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
+#define KS2_ETHERNET_CFG		(KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
+#define KS2_ETHERNET_RGMII		2
 
 /* PSC */
 #define KS2_PSC_BASE			0x02350000
 #define KS2_LPSC_GEM_0			15
 #define KS2_LPSC_TETRIS			52
 #define KS2_TETRIS_PWR_DOMAIN		31
+#define KS2_GEM_0_PWR_DOMAIN		8
 
 /* Chip configuration unlock codes and registers */
 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
@@ -167,6 +179,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_UARTPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x390)
+#define KS2_UARTPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x394)
 
 #define KS2_PLL_CNTRL_BASE		0x02310000
 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
@@ -179,10 +193,17 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_RSTYPE_PLL_SOFT		BIT(13)
 
 /* SPI */
+#ifdef CONFIG_SOC_K2G
+#define KS2_SPI0_BASE			0x21805400
+#define KS2_SPI1_BASE			0x21805800
+#define KS2_SPI2_BASE			0x21805c00
+#define KS2_SPI3_BASE			0x21806000
+#else
 #define KS2_SPI0_BASE			0x21000400
 #define KS2_SPI1_BASE			0x21000600
 #define KS2_SPI2_BASE			0x21000800
 #define KS2_SPI_BASE			KS2_SPI0_BASE
+#endif
 
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
@@ -194,10 +215,16 @@ typedef volatile unsigned int   *dv_reg_p;
 /* MSMC control */
 #define KS2_MSMC_CTRL_BASE		0x0bc00000
 #define KS2_MSMC_DATA_BASE		0x0c000000
+#ifndef CONFIG_SOC_K2G
 #define KS2_MSMC_SEGMENT_TETRIS		8
 #define KS2_MSMC_SEGMENT_NETCP		9
 #define KS2_MSMC_SEGMENT_QM_PDSP	10
 #define KS2_MSMC_SEGMENT_PCIE0		11
+#else
+#define KS2_MSMC_SEGMENT_TETRIS		1
+#define KS2_MSMC_SEGMENT_NETCP		4
+#define KS2_MSMC_SEGMENT_PCIE0		5
+#endif
 
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
@@ -211,6 +238,22 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
 /* Queue manager */
+#ifdef CONFIG_SOC_K2G
+#define KS2_QM_BASE_ADDRESS		0x040C0000
+#define KS2_QM_CONF_BASE		0x04040000
+#define KS2_QM_DESC_SETUP_BASE		0x04080000
+#define KS2_QM_STATUS_RAM_BASE		0x0 /* K2G doesn't have it */
+#define KS2_QM_INTD_CONF_BASE		0x0
+#define KS2_QM_PDSP1_CMD_BASE		0x0
+#define KS2_QM_PDSP1_CTRL_BASE		0x0
+#define KS2_QM_PDSP1_IRAM_BASE		0x0
+#define KS2_QM_MANAGER_QUEUES_BASE	0x040c0000
+#define KS2_QM_MANAGER_Q_PROXY_BASE	0x04040200
+#define KS2_QM_QUEUE_STATUS_BASE	0x04100000
+#define KS2_QM_LINK_RAM_BASE		0x04020000
+#define KS2_QM_REGION_NUM		8
+#define KS2_QM_QPOOL_NUM		112
+#else
 #define KS2_QM_BASE_ADDRESS		0x23a80000
 #define KS2_QM_CONF_BASE		0x02a02000
 #define KS2_QM_DESC_SETUP_BASE		0x02a03000
@@ -225,6 +268,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_QM_LINK_RAM_BASE		0x00100000
 #define KS2_QM_REGION_NUM		64
 #define KS2_QM_QPOOL_NUM		4000
+#endif
 
 /* USB */
 #define KS2_USB_SS_BASE			0x02680000
@@ -247,6 +291,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define CPU_66AK2Hx	0xb981
 #define CPU_66AK2Ex	0xb9a6
 #define CPU_66AK2Lx	0xb9a7
+#define CPU_66AK2Gx	0xbb06
 
 /* DEVSPEED register */
 #define DEVSPEED_DEVSPEED_SHIFT	16
@@ -267,6 +312,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #include <asm/arch/hardware-k2l.h>
 #endif
 
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/hardware-k2g.h>
+#endif
+
 #ifndef __ASSEMBLY__
 
 static inline u16 get_part_number(void)
@@ -291,6 +340,11 @@ static inline u8 cpu_is_k2l(void)
 	return get_part_number() == CPU_66AK2Lx;
 }
 
+static inline u8 cpu_is_k2g(void)
+{
+	return get_part_number() == CPU_66AK2Gx;
+}
+
 static inline u8 cpu_revision(void)
 {
 	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);