X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-keystone%2Fclock.c;h=5c6051e76db88807734b910010c659414060a23b;hb=225217da2804d1c61725e2974262bd2f27882cd7;hp=6cb646734a18093d5a987e3c225423a7e6c341a4;hpb=7003e4cf76138de2f6af2f251ec929f2ea4b4043;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 6cb646734a..5c6051e76d 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -31,6 +31,7 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
 	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+	[UART_PLL]	= {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
 };
 
 inline void pll_pa_clk_sel(void)
@@ -313,6 +314,10 @@ static unsigned long pll_freq_get(int pll)
 			ret = external_clk[ddr3b_clk];
 			reg = KS2_DDR3BPLLCTL0;
 			break;
+		case UART_PLL:
+			ret = external_clk[uart_clk];
+			reg = KS2_UARTPLLCTL0;
+			break;
 		default:
 			return 0;
 		}
@@ -355,6 +360,10 @@ unsigned long clk_get_rate(unsigned int clk)
 		if (cpu_is_k2hk())
 			freq = pll_freq_get(DDR3B_PLL);
 		break;
+	case uart_pll_clk:
+		if (cpu_is_k2g())
+			freq = pll_freq_get(UART_PLL);
+		break;
 	case sys_clk0_1_clk:
 	case sys_clk0_clk:
 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);