X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-imx%2Fimx8%2Fcpu.c;h=38b2c0926f58a3258341129a46884a484fd25433;hb=60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22;hp=7599afe720327015db51b9d0be88b8cfd7c0577c;hpb=e5aa3f4d97b11271c3a2407e272a131b7e975c61;p=oweals%2Fu-boot.git diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 7599afe720..38b2c0926f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -6,17 +6,25 @@ #include #include #include +#include #include +#include +#include +#include #include #include #include #include +#include +#include #include #include #include #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -35,15 +43,24 @@ struct pass_over_info_t *get_pass_over_info(void) int arch_cpu_init(void) { - struct pass_over_info_t *pass_over = get_pass_over_info(); - - if (pass_over && pass_over->g_ap_mu == 0) { - /* - * When ap_mu is 0, means the U-Boot booted - * from first container - */ - sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) + spl_save_restore_data(); +#endif + +#ifdef CONFIG_SPL_BUILD + struct pass_over_info_t *pass_over; + + if (is_soc_rev(CHIP_REV_A)) { + pass_over = get_pass_over_info(); + if (pass_over && pass_over->g_ap_mu == 0) { + /* + * When ap_mu is 0, means the U-Boot booted + * from first container + */ + sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS); + } } +#endif return 0; } @@ -54,18 +71,18 @@ int arch_cpu_init_dm(void) int node, ret; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); - ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu", - offset_to_ofnode(node), &devp); + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); if (ret) { - printf("could not find scu %d\n", ret); + printf("could not get scu %d\n", ret); return ret; } - ret = device_probe(devp); - if (ret) { - printf("scu probe failed %d\n", ret); - return ret; + if (is_imx8qm()) { + ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU, + SC_PM_PW_MODE_ON); + if (ret) + return ret; } return 0; @@ -154,6 +171,37 @@ enum boot_device get_boot_device(void) return boot_dev; } +#ifdef CONFIG_SERIAL_TAG +#define FUSE_UNIQUE_ID_WORD0 16 +#define FUSE_UNIQUE_ID_WORD1 17 +void get_board_serial(struct tag_serialnr *serialnr) +{ + sc_err_t err; + u32 val1 = 0, val2 = 0; + u32 word1, word2; + + if (!serialnr) + return; + + word1 = FUSE_UNIQUE_ID_WORD0; + word2 = FUSE_UNIQUE_ID_WORD1; + + err = sc_misc_otp_fuse_read(-1, word1, &val1); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word1, err); + return; + } + + err = sc_misc_otp_fuse_read(-1, word2, &val2); + if (err != SC_ERR_NONE) { + printf("%s fuse %d read error: %d\n", __func__, word2, err); + return; + } + serialnr->low = val1; + serialnr->high = val2; +} +#endif /*CONFIG_SERIAL_TAG*/ + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { @@ -215,7 +263,7 @@ static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, phys_size_t get_effective_memsize(void) { sc_rm_mr_t mr; - sc_faddr_t start, end, end1; + sc_faddr_t start, end, end1, start_aligned; int err; end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; @@ -223,9 +271,9 @@ phys_size_t get_effective_memsize(void) for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { - start = roundup(start, MEMSTART_ALIGNMENT); + start_aligned = roundup(start, MEMSTART_ALIGNMENT); /* Too small memory region, not use it */ - if (start > end) + if (start_aligned > end) continue; /* Find the memory region runs the U-Boot */ @@ -441,7 +489,7 @@ void enable_caches(void) dcache_enable(); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); @@ -469,10 +517,17 @@ u64 get_page_table_size(void) } #endif +#if defined(CONFIG_IMX8QM) +#define FUSE_MAC0_WORD0 452 +#define FUSE_MAC0_WORD1 453 +#define FUSE_MAC1_WORD0 454 +#define FUSE_MAC1_WORD1 455 +#elif defined(CONFIG_IMX8QXP) #define FUSE_MAC0_WORD0 708 #define FUSE_MAC0_WORD1 709 #define FUSE_MAC1_WORD0 710 #define FUSE_MAC1_WORD1 711 +#endif void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { @@ -507,15 +562,6 @@ err: printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); } -#if CONFIG_IS_ENABLED(CPU) -struct cpu_imx_platdata { - const char *name; - const char *rev; - const char *type; - u32 cpurev; - u32 freq_mhz; -}; - u32 get_cpu_rev(void) { u32 id = 0, rev = 0; @@ -531,116 +577,43 @@ u32 get_cpu_rev(void) return (id << 12) | rev; } -const char *get_imx8_type(u32 imxtype) +void board_boot_order(u32 *spl_boot_list) { - switch (imxtype) { - case MXC_CPU_IMX8QXP: - case MXC_CPU_IMX8QXP_A0: - return "QXP"; - default: - return "??"; - } -} + spl_boot_list[0] = spl_boot_device(); -const char *get_imx8_rev(u32 rev) -{ - switch (rev) { - case CHIP_REV_A: - return "A"; - case CHIP_REV_B: - return "B"; - default: - return "?"; + if (spl_boot_list[0] == BOOT_DEVICE_SPI) { + /* Check whether we own the flexspi0, if not, use NOR boot */ + if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) + spl_boot_list[0] = BOOT_DEVICE_NOR; } } -const char *get_core_name(void) -{ - if (is_cortex_a35()) - return "A35"; - else if (is_cortex_a53()) - return "A53"; - else if (is_cortex_a72()) - return "A72"; - else - return "?"; -} - -int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) -{ - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - - if (size < 100) - return -ENOSPC; - - snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n", - plat->type, plat->rev, plat->name, plat->freq_mhz); - - return 0; -} - -static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info) +bool m4_parts_booted(void) { - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - - info->cpu_freq = plat->freq_mhz * 1000; - info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); - return 0; -} - -static int cpu_imx_get_count(struct udevice *dev) -{ - return 4; -} - -static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size) -{ - snprintf(buf, size, "NXP"); - return 0; -} - -static const struct cpu_ops cpu_imx8_ops = { - .get_desc = cpu_imx_get_desc, - .get_info = cpu_imx_get_info, - .get_count = cpu_imx_get_count, - .get_vendor = cpu_imx_get_vendor, -}; + sc_rm_pt_t m4_parts[2]; + int err; -static const struct udevice_id cpu_imx8_ids[] = { - { .compatible = "arm,cortex-a35" }, - { } -}; + err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]); + if (err) { + printf("%s get resource [%d] owner error: %d\n", __func__, + SC_R_M4_0_PID0, err); + return false; + } -static int imx8_cpu_probe(struct udevice *dev) -{ - struct cpu_imx_platdata *plat = dev_get_platdata(dev); - struct clk cpu_clk; - u32 cpurev; - int ret; + if (sc_pm_is_partition_started(-1, m4_parts[0])) + return true; - cpurev = get_cpu_rev(); - plat->cpurev = cpurev; - plat->name = get_core_name(); - plat->rev = get_imx8_rev(cpurev & 0xFFF); - plat->type = get_imx8_type((cpurev & 0xFF000) >> 12); + if (is_imx8qm()) { + err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]); + if (err) { + printf("%s get resource [%d] owner error: %d\n", + __func__, SC_R_M4_1_PID0, err); + return false; + } - ret = clk_get_by_index(dev, 0, &cpu_clk); - if (ret) { - debug("%s: Failed to get CPU clk: %d\n", __func__, ret); - return 0; + if (sc_pm_is_partition_started(-1, m4_parts[1])) + return true; } - plat->freq_mhz = clk_get_rate(&cpu_clk) / 1000000; - return 0; + return false; } - -U_BOOT_DRIVER(cpu_imx8_drv) = { - .name = "imx8x_cpu", - .id = UCLASS_CPU, - .of_match = cpu_imx8_ids, - .ops = &cpu_imx8_ops, - .probe = imx8_cpu_probe, - .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata), - .flags = DM_FLAG_PRE_RELOC, -}; -#endif